Concurrent Parallel XIP Flash and SRAM Design for code download & execution on High Performance MCUs
TIDM-TM4CFLASHSRAM
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
See the Important Notice and Disclaimer covering reference designs and other TI resources.
Key Document
- Concurrent Parallel XIP Flash and SRAM Design for Code Download Design Guide
(PDF 2007 KB)
01 Jun 2015
Description
This reference design demonstrates how to implement and interface Asynchronous Parallel Flash and SRAM Memories to the performance microcontroller TM4C129. The implementation is made possible by using the EPI Interface in Host Bus 16 Mode with mutliple Chip Selects to interface a 1Gbit-8Mbit range 16-bit Parallel Flash and 16Mbit 16-bit Parallel SRAM allowing developers to expand code and data space above the maximum Internal Memory of the TM4C1294 microcontroller.
Features
- Extend the useable memory space to 1Gbit 16-bit FLASH and 16Mbit 16-bit Asynchronous SRAM with the 60MHz External Peripherial Interface (EPI) for large memory footprint applications
- Designed for (formerly Tiva MCU) EK-TM4C1294XL Connected LaunchPad
- Implements Serial boot loader for Programming Parallel Flash in-situ over EPI
- Supports detection of Flash and SRAM connected to EPI
- Scalable Flash Footprint design from 64Mbit to 1Gbit
- Source code contains project examples for Code Composer Studio
See the Important Notice and Disclaimer covering reference designs and other TI resources.
