This reference design demonstrates how to implement and interface Asynchronous Parallel Flash and SRAM Memories to the performance microcontroller TM4C129. The implementation is made possible by using the EPI Interface in Host Bus 16 Mode with mutliple Chip Selects to interface a 1Gbit-8Mbit range 16-bit Parallel Flash and 16Mbit 16-bit Parallel SRAM allowing developers to expand code and data space above the maximum Internal Memory of the TM4C1294 microcontroller.
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Design file that contains information on physical board layer of design PCB
Includes TI products in the design and potential alternatives.
The TM4C1294 Connected LaunchPad Evaluation Kit is a low-cost development platform for ARM® Cortex-M4F-based microcontrollers. The Connected LaunchPad design highlights the TM4C1294NCPDT MCU with its on-chip 10/100 Ethernet MAC and PHY, USB 2.0, hibernation module, motion control pulse-width (...)
| Type | Title | Date | |
|---|---|---|---|
| * | Design guide | Concurrent Parallel XIP Flash and SRAM Design for Code Download Design Guide | Jun. 01, 2015 |
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