RF PLLs & synthesizers – Technical documents
RF phase locked loop (PLL) and synthesizers selection guides, application notes, white papers, and much more.
PLL Performance Simulation and Design Handbook
A unique approach to PLL design combining rigorous mathematical derivations for formulas with actual measured data.
PLL and RF Synthesizer Solutions (Rev. C)
Our RF phase-locked loop (PLL) and synthesizers deliver leading-edge performance in industrial, communications, and automotive systems.
Clock & Timing Solutions (Rev. C)
Learn more about our comprehensive and flexible portfolio of clock oscillators, clock generators, clock buffers, clock jitter cleaners, RF PLLs and synthesizers.
Featured application notes
LMX2571 Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs
Using a programmable input multiplier allows the spurs of a PLL to be drastically improved, especially for the worst case VCO frequencies. This feature is included on some of our PLLs, such as the LMX2571, LMX2582 and LMX2592.
Clocking Optimization for RF Sampling Analog-to-Digital Converters
When designing a system with an ADC, make sure that the jitter of the clock does not degrade the signal-to-noise ratio of the ADC. High-performance synthesizers used with RF sampling ADCs get the best system performance.
Application notes
Showing 3 of 22 results View All 22 Results
| Title | Type | Size (KB) | Date |
|---|---|---|---|
| Achieving Low Frequency Switchover Time for Wireless Infrastructure Applications | 1312 | 28 Nov 2018 | |
| Frequency Shift Keying with LMX2571 | 267 | 30 May 2017 | |
| RF Sampling ADC with 800MHz of IBW LTE | 846 | 08 Sep 2016 |
Selection guides
Showing 3 of 3 results
| Title | Type | Size (KB) | Date |
|---|---|---|---|
| PLL and RF Synthesizer Solutions (Rev. C) | 5321 | 02 May 2017 | |
| TI Components for Aerospace and Defense Guide (Rev. E) | 9699 | 22 Mar 2017 | |
| Clock & Timing Applications (Rev. B) | 547 | 21 Dec 2015 |