RF PLLs and Synthesizers – Technical documents
RF phase locked loop (PLL) and synthesizers selection guides, application notes, white papers, and much more.
A unique approach to PLL design combining rigorous mathematical derivations for formulas with actual measured data.
Featured application notes
Using a programmable input multiplier allows the spurs of a PLL to be drastically improved, especially for the worst case VCO frequencies. This feature is included on some TI PLLs, such as the LMX2571, LMX2582, and LMX2592.
When designing a system with an ADC, it is important to ensure the jitter of the clock doesn’t degrade the Signal-to-Noise ratio of the ADC. High performance synthesizers used with RF sampling ADCs get the best system performance.
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|Frequency Shift Keying with LMX2571||Read Abstract||8||30 May 2017||571|
|RF Sampling ADC with 800MHz of IBW LTE||846||08 Sep 2016||733|
|Clocking Optimization for RF Sampling Analog-to-Digital Converters||Read Abstract||8||17 May 2016||453|
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|PLL and RF Synthesizer Solutions (Rev. C)||5321||02 May 2017||5553|
|TI Components for Aerospace and Defense Guide (Rev. E)||9699||22 Mar 2017||4507|
|Clock & Timing Applications (Rev. B)||547||21 Dec 2015||535|
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|2016 Automotive Infotainment Guide (Rev. D)||1248||01 Jun 2016||10885|
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