Clock and Timing

RF PLLs and Synthesizers – Technical documents

RF phase locked loop (PLL) and synthesizers selection guides, application notes, white papers, and much more.

PLL Performance Simulation and Design Handbook

A unique approach to PLL design combining rigorous mathematical derivations for formulas with actual measured data.

PLL and RF Synthesizer Solutions (Rev. C)

TI's RF phase locked loop (PLL) and synthesizers deliver leading-edge performance in industrial, communications, and automotive systems.

Clock & Timing Solutions (Rev. C)

Comprehensive, flexible portfolio of clock oscillators, clock generators, clock buffers, clock jitter cleaners, and RF PLLs/synthesizers.

Featured application notes

Using a Programmable Input Multiplier to Minimize Integer Boundary Spurs

Using a programmable input multiplier allows the spurs of a PLL to be drastically improved, especially for the worst case VCO frequencies. This feature is included on some TI PLLs, such as the LMX2571, LMX2582, and LMX2592.

Clocking Optimization for RF Sampling Analog-to-Digital Converters

When designing a system with an ADC, it is important to ensure the jitter of the clock doesn’t degrade the Signal-to-Noise ratio of the ADC. High performance synthesizers used with RF sampling ADCs get the best system performance.

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Application notes

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Title Abstract Type Size (KB) Date
Frequency Shift Keying with LMX2571 Read Abstract PDF 8 30 May 2017
RF Sampling ADC with 800MHz of IBW LTE PDF 846 08 Sep 2016
Clocking Optimization for RF Sampling Analog-to-Digital Converters Read Abstract PDF 8 17 May 2016

Selection guides

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Title Abstract Type Size (KB) Date
PLL and RF Synthesizer Solutions (Rev. C) PDF 5321 02 May 2017
TI Components for Aerospace and Defense Guide (Rev. E) PDF 9699 22 Mar 2017
Clock & Timing Applications (Rev. B) PDF 547 21 Dec 2015

Solution guides

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White papers

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