SLVSF11 June 2019 TPS652170
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
DEFSLEW is shown in Figure 47 and described in Table 19.
Return to Summary Table.
Slew-rate control applies to all three DC/DC converters.
This register is password protected.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
GO | GODSBL | PFM_EN1 | PFM_EN2 | PFM_EN3 | SLEW[2:0] | ||
R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-110b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | GO | R/W | 0b |
Go bit
0b = No change 1b = Initiates the transition from the present state to the output voltage setting currently stored in the DEFDCDCx register |
6 | GODSBL | R/W | 0b |
Go Disable bit 0b = Enabled 1b = Disabled; DCDCx output voltage changes whenever setpoint is updated in DEFDCDCx register without having to write to the GO bit. SLEW[2:0] setting does apply. |
5 | PFM_EN1 | R/W | 0b |
PFM enable bit, DCDC1 0b = DC/DC converter operates in the PWM or PFM mode, depending on load. 1b = DC/DC converter is forced into the fixed-frequency PWM mode. |
4 | PFM_EN2 | R/W | 0b |
PFM enable bit, DCDC2 0b = DC/DC converter operates in the PWM or PFM mode, depending on load. 1b = DC/DC converter is forced into the fixed-frequency PWM mode. |
3 | PFM_EN3 | R/W | 0b |
PFM enable bit, DCDC3 0b = DC/DC converter operates in the PWM or PFM mode, depending on load. 1b = DC/DC converter is forced into the fixed-frequency PWM mode. |
2–0 | SLEW[2:0] | R/W | 0110b |
Output slew-rate setting
000b = 224 µs/step (0.11 mV/µs at 25 mV per step) 001b = 112 µs/step (0.22 mV/µs at 25 mV per step) 010b = 56 µs/step (0.45 mV/µs at 25 mV per step) 011b = 28 µs/step (0.90 mV/µs at 25 mV per step) 100b = 14 µs/step (1.80 mV/µs at 25 mV per step) 101b = 7 µs/step (3.60 mV/µs at 25 mV per step) 110b = 3.5 µs/step (7.2 mV/µs at 25 mV per step) 111b = Immediate; slew rate is only limited by the control loop response time. |