SLVSF06 March   2019 TPS65653-Q1

PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.  

  1. 1 Features
    1.     Simplified Schematic
  2. 2 Applications
  3. 3 Description
    1.     DC/DC Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
        2. 7.3.4.2 Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
          1. 7.3.7.1.1 PGOOD Pin Gated mode
          2. 7.3.7.1.2 PGOOD Pin Continuous Mode
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 Operation of the GPO Signals
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  BUCK0_DELAY
        10. 7.6.1.10 BUCK1_DELAY
        11. 7.6.1.11 GPO_DELAY
        12. 7.6.1.12 GPO2_DELAY
        13. 7.6.1.13 GPO_CTRL
        14. 7.6.1.14 CONFIG
        15. 7.6.1.15 PLL_CTRL
        16. 7.6.1.16 PGOOD_CTRL_1
        17. 7.6.1.17 PGOOD_CTRL_2
        18. 7.6.1.18 PG_FAULT
        19. 7.6.1.19 RESET
        20. 7.6.1.20 INT_TOP_1
        21. 7.6.1.21 INT_TOP_2
        22. 7.6.1.22 INT_BUCK
        23. 7.6.1.23 TOP_STAT
        24. 7.6.1.24 BUCK_STAT
        25. 7.6.1.25 TOP_MASK_1
        26. 7.6.1.26 TOP_MASK_2
        27. 7.6.1.27 BUCK_MASK
        28. 7.6.1.28 SEL_I_LOAD
        29. 7.6.1.29 I_LOAD_2
        30. 7.6.1.30 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.7 Diagnosis and Protection Features

The TPS65653-Q1 is capable of providing four levels of protection features:

  • Information of valid regulator output voltage which sets interrupt or PGOOD signal;
  • Warnings for diagnosis which sets interrupt;
  • Protection events which are disabling the regulators; and
  • Faults which are causing the device to shutdown.

The TPS65653-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared.

When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded from OTP during reset sequence.

Table 4. Summary of Interrupt Signals

EVENT OUTCOME INTERRUPT BIT INTERRUPT MASK BIT STATUS BIT RECOVERY/INTERRUPT CLEAR
Buck current limit triggered No effect BUCK_INT
BUCKx_ILIM_INT		 BUCKx_ILIM_MASK BUCKx_ILIM_STAT Write 1 to BUCKx_ILIM_INT bit
Interrupt is not cleared if current limit is active
Buck short circuit (VOUT < 0.35 V at 1 ms after enable) or overload (VOUT decreasing below 0.35 V during operation, 1-ms debounce) Regulator disable BUCK_INT
BUCKx_SC_INT		 N/A N/A Write 1 to BUCKx_SC_INT bit
Thermal warning No effect TDIE_WARN_INT TDIE_WARN_MASK TDIE_WARN_STAT Write 1 to TDIE_WARN_INT bit
Interrupt is not cleared if temperature is above thermal warning level
Thermal shutdown All regulators disabled immediately and GPO and GPO2 are set to low TDIE_SD_INT N/A TDIE_SD_STAT Write 1 to TDIE_SD_INT bit
Interrupt is not cleared if temperature is above thermal shutdown level
VANA overvoltage (VANAOVP) All regulators disabled immediately and GPO and GPO2 are set to low OVP_INT N/A OVP_STAT Write 1 to OVP_INT bit
Interrupt is not cleared if VANA voltage is above VANAOVP level
Buck power good, output voltage becomes valid No effect BUCK_INT
BUCKx_PG_INT		 BUCKx_PGR_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit
Buck power good, output voltage becomes invalid No effect BUCK_INT
BUCKx_PG_INT		 BUCKx_PGF_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit
PGOOD pin changing from active to inactive state(1) No effect PGOOD_INT PGOOD_MASK PGOOD_STAT Write 1 to PGOOD_INT bit
External clock appears or disappears No effect to regulators SYNC_CLK_INT(2) SYNC_CLK_MASK SYNC_CLK_STAT Write 1 to SYNC_CLK_INT bit
Load current measurement ready No effect I_MEAS_INT I_MEAS_MASK N/A Write 1 to I_MEAS_INT bit
Supply voltage VANAUVLO triggered (VANA falling) Immediate shutdown, registers reset to default values N/A N/A N/A N/A
Supply voltage VANAUVLO triggered (VANA rising) Startup, registers reset to default values and OTP bits loaded RESET_REG_INT RESET_REG_MASK N/A Write 1 to RESET_REG_INT bit
Software requested reset Immediate shutdown followed by power up, registers reset to default values RESET_REG_INT RESET_REG_MASK N/A Write 1 to RESET_REG_INT bit
(1) PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. PGOOD_POL bit in PGOOD_CTRL_1 register affects only PGOOD pin polarity, not Power Good and PGOOD_INT interrupt polarity.
(2) Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled.