SLVSF06 March   2019 TPS65653-Q1

PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.  

  1. 1 Features
    1.     Simplified Schematic
  2. 2 Applications
  3. 3 Description
    1.     DC/DC Efficiency vs Output Current
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Serial Bus Timing Parameters
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 DC/DC Converters
        1. 7.3.1.1 Overview
        2. 7.3.1.2 Transition Between PWM and PFM Modes
        3. 7.3.1.3 Buck Converter Load Current Measurement
        4. 7.3.1.4 Spread-Spectrum Mode
      2. 7.3.2 Sync Clock Functionality
      3. 7.3.3 Power-Up
      4. 7.3.4 Regulator Control
        1. 7.3.4.1 Enabling and Disabling Regulators
        2. 7.3.4.2 Changing Output Voltage
      5. 7.3.5 Enable and Disable Sequences
      6. 7.3.6 Device Reset Scenarios
      7. 7.3.7 Diagnosis and Protection Features
        1. 7.3.7.1 Power-Good Information (PGOOD pin)
          1. 7.3.7.1.1 PGOOD Pin Gated mode
          2. 7.3.7.1.2 PGOOD Pin Continuous Mode
        2. 7.3.7.2 Warnings for Diagnosis (Interrupt)
          1. 7.3.7.2.1 Output Power Limit
          2. 7.3.7.2.2 Thermal Warning
        3. 7.3.7.3 Protection (Regulator Disable)
          1. 7.3.7.3.1 Short-Circuit and Overload Protection
          2. 7.3.7.3.2 Overvoltage Protection
          3. 7.3.7.3.3 Thermal Shutdown
        4. 7.3.7.4 Fault (Power Down)
          1. 7.3.7.4.1 Undervoltage Lockout
      8. 7.3.8 Operation of the GPO Signals
      9. 7.3.9 Digital Signal Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
    5. 7.5 Programming
      1. 7.5.1 I2C-Compatible Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 Start and Stop Conditions
        3. 7.5.1.3 Transferring Data
        4. 7.5.1.4 I2C-Compatible Chip Address
        5. 7.5.1.5 Auto-Increment Feature
    6. 7.6 Register Maps
      1. 7.6.1 Register Descriptions
        1. 7.6.1.1  DEV_REV
        2. 7.6.1.2  OTP_REV
        3. 7.6.1.3  BUCK0_CTRL_1
        4. 7.6.1.4  BUCK0_CTRL_2
        5. 7.6.1.5  BUCK1_CTRL_1
        6. 7.6.1.6  BUCK1_CTRL_2
        7. 7.6.1.7  BUCK0_VOUT
        8. 7.6.1.8  BUCK1_VOUT
        9. 7.6.1.9  BUCK0_DELAY
        10. 7.6.1.10 BUCK1_DELAY
        11. 7.6.1.11 GPO_DELAY
        12. 7.6.1.12 GPO2_DELAY
        13. 7.6.1.13 GPO_CTRL
        14. 7.6.1.14 CONFIG
        15. 7.6.1.15 PLL_CTRL
        16. 7.6.1.16 PGOOD_CTRL_1
        17. 7.6.1.17 PGOOD_CTRL_2
        18. 7.6.1.18 PG_FAULT
        19. 7.6.1.19 RESET
        20. 7.6.1.20 INT_TOP_1
        21. 7.6.1.21 INT_TOP_2
        22. 7.6.1.22 INT_BUCK
        23. 7.6.1.23 TOP_STAT
        24. 7.6.1.24 BUCK_STAT
        25. 7.6.1.25 TOP_MASK_1
        26. 7.6.1.26 TOP_MASK_2
        27. 7.6.1.27 BUCK_MASK
        28. 7.6.1.28 SEL_I_LOAD
        29. 7.6.1.29 I_LOAD_2
        30. 7.6.1.30 I_LOAD_1
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Inductor Selection
        2. 8.2.1.2 Buck Input Capacitor Selection
        3. 8.2.1.3 Buck Output Capacitor Selection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.1 Register Descriptions

The TPS65653-Q1 is controlled by a set of registers through the I2C-compatible interface. The device registers, their addresses and their abbreviations are listed in Table 7. A more detailed description is given in the DEV_REV to I_LOAD_1 sections.

An "X" indicates register bits which are updated from OTP memory during READ OTP state.

Table 7. Summary of TPS65653-Q1 Control Registers

Addr Register Read / Write D7 D6 D5 D4 D3 D2 D1 D0
0x00 DEV_REV R DEVICE_ID[1:0] Reserved
0x01 OTP_REV R OTP_ID[7:0]
0x02 BUCK0_
CTRL_1		 R/W Reserved BUCK0_FPWM BUCK0_RDIS_EN BUCK0_
EN_PIN_CTRL		 BUCK0_EN
0x03 BUCK0_
CTRL_2		 R/W Reserved BUCK0_ILIM[2:0] BUCK0_SLEW_RATE[2:0]
0x04 BUCK1_
CTRL_1		 R/W Reserved BUCK1_FPWM BUCK1_RDIS_EN BUCK1_
EN_PIN_CTRL		 BUCK1_EN
0x05 BUCK1_
CTRL_2		 R/W Reserved BUCK1_ILIM[2:0] BUCK1_SLEW_RATE[2:0]
0x06 BUCK0_
VOUT		 R/W BUCK0_VSET[7:0]
0x07 BUCK1_
VOUT		 R/W BUCK1_VSET[7:0]
0x0C BUCK0_
DELAY		 R/W BUCK0_SHUTDOWN_DELAY[3:0] BUCK0_STARTUP_DELAY[3:0]
0x0D BUCK1_
DELAY		 R/W BUCK1_SHUTDOWN_DELAY[3:0] BUCK1_STARTUP_DELAY[3:0]
0x10 GPO_
DELAY		 R/W GPO_SHUTDOWN_DELAY[3:0] GPO_STARTUP_DELAY[3:0]
0x11 GPO2_
DELAY		 R/W GPO2_SHUTDOWN_DELAY[3:0] GPO2_STARTUP_DELAY[3:0]
0x12 GPO_
CTRL		 R/W Reserved GPO2_OD GPO2_
EN_PIN_CTRL		 GPO2_EN Reserved GPO_OD GPO_
EN_PIN_CTRL		 GPO_EN
0x13 CONFIG R/W Reserved STARTUP_DELAY_SEL SHUTDOWN_DELAY_SEL CLKIN_PIN_SEL CLKIN_PD EN_PD TDIE
_WARN
_LEVEL		 EN_
SPREAD
_SPEC
0x14 PLL_CTRL R/W Reserved EN_PLL Reserved EXT_CLK_FREQ[4:0]
0x15 PGOOD_CTRL_1 R/W PGOOD_POL PGOOD_OD Reserved PGOOD_WINDOW_BUCK Reserved EN_PGOOD_BUCK1 EN_PGOOD_BUCK0
0x16 PGOOD_CTRL_2 R/W Reserved EN_PGOOD_TWARN PG_FAULT_GATES_PGOOD PGOOD_MODE
0x17 PG_FAULT R Reserved PG_FAULT_BUCK1 PG_FAULT_BUCK0
0x18 RESET R/W Reserved SW_
RESET
0x19 INT_TOP_1 R/W PGOOD_
INT		 Reserved INT_
BUCK		 SYNC_
CLK_INT		 TDIE_SD_INT TDIE_
WARN_INT		 OVP_INT I_MEAS_
INT
0x1A INT_TOP_2 R/W Reserved RESET_
REG_INT
0x1B INT_BUCK R/W Reserved BUCK1_
PG_INT		 BUCK1_
SC_INT		 BUCK1_
ILIM_INT		 Reserved BUCK0_
PG_INT		 BUCK0_
SC_INT		 BUCK0_
ILIM_INT
0x1D TOP_
STAT		 R PGOOD_STAT Reserved SYNC_CLK
_STAT		 TDIE_SD
_STAT		 TDIE_
WARN_
STAT		 OVP_
STAT		 Reserved
0x1E BUCK_STAT R BUCK1_
STAT		 BUCK1_
PG_STAT		 Reserved BUCK1_
ILIM_STAT		 BUCK0_
STAT		 BUCK0_
PG_STAT		 Reserved BUCK0_
ILIM_STAT
0x20 TOP_
MASK_1		 R/W PGOOD_
INT_MASK		 Reserved SYNC_CLK
_MASK		 Reserved TDIE_WARN_MASK Reserved I_MEAS_
MASK
0x21 TOP_
MASK_2		 R/W Reserved RESET_
REG_MASK
0x22 BUCK_MASK R/W BUCK1_PGF_MASK BUCK1_PGR_MASK Reserved BUCK1_
ILIM_
MASK		 BUCK0_PGF_MASK BUCK0_PGR_MASK Reserved BUCK0_
ILIM_
MASK
0x24 SEL_I_
LOAD		 R/W Reserved LOAD_CURRENT_
BUCK_SELECT
0x25 I_LOAD_2 R Reserved BUCK_LOAD_CURRENT[8]
0x26 I_LOAD_1 R BUCK_LOAD_CURRENT[7:0]