SLVSF06 March 2019 TPS65653-Q1
PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice.
When the input voltage falls below VANAUVLO at the VANA pin, the buck regulators are disabled immediately (without switching ramp, no shutdown delays), and the output capacitor is discharged using the pulldown resistor, and the TPS65653-Q1 device enters SHUTDOWN. When V(VANA) voltage is above VANAUVLO threshold level, the device powers up to STANDBY state.
If the reset interrupt is unmasked by default (OTP bit for RESET_REG_MASK is 0 in TOP_MASK_2 register) the RESET_REG_INT interrupt bit in INT_TOP_2 register indicates that the device has been in SHUTDOWN. The host processor must clear the interrupt by writing 1 to the RESET_REG_INT bit. If the host processor reads the RESET_REG_INT interrupt bit after detecting an nINT low signal, it knows that the input supply voltage has been below VANAUVLO level (or the host has requested reset with SW_RESET bit in RESET register), and the registers are reset to default values.