7.3.7.1.1 PGOOD Pin Gated mode
The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2 register.
For the gated mode of operation, PGOOD behaves as follows:
- PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.
- PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status indication.
- During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an 800-µs gated time period. It typically remains active or asserted for normal conditions.
- During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.
- Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit configuration provides a smart PORz function for processor that eliminates the need for additional components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.
The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 11.