JAJSM24A December   2023  – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Register Descriptions

Table 6-5 DEVICE Registers
AddressRegister Name
0hRESET
38hCFG_ALERT
39hSPARE_REG
84hINTERLEAVE
85hREF_EQ
88hDEV_CFG_1
89hDEV_CFG_2
8AhCLK_CFG_1
8BhCLK_CFG_2
8ChPDN_CFG
8DhDEV_CFG_3
8EhCLK_CFG_3
8FhCLK_CFG_4
90hPIN_CFG_1
91hTEST_PAT_CFG
91hTEST_PATTERN_CFG
92hTEST_PATTERN_CHB_7:0
93hTEST_PATTERN_CHB_13:8
94hTEST_PATTERN_CHA_7:0
95hTEST_PATTERN_CHA_13:8
97hGLOBAL_PDN
98hINTERFACE_CFG_1
9ChINTERFACE_CFG_2
9EhHFSB_FPDN_CFG
A0hINTERFACE_CFG_3
A1hDIG_PATTERN_EN
A2hDIG_PATTERN_CHA_7:0
A3hDIG_PATTERN_CHA_15:8
A4hDIG_PATTERN_CHB_7:0
A5hDIG_PATTERN_CHB_15:8
A6hINTERFACE_CFG_4
A7hOUTPUT_DATA_WIDTH
A8hDCLK_DIVIDER
AEhOUTPUT_BIT_MAPPER_D0_D1
AFhOUTPUT_BIT_MAPPER_D2_D3
B0hOUTPUT_BIT_MAPPER_D4_D5
B1hOUTPUT_BIT_MAPPER_D6_D7
B2hOUTPUT_BIT_MAPPER_D8_D9
B3hOUTPUT_BIT_MAPPER_D10_D11
B6hROUND
C8hCOMP_THRESHOLD_HI_CHA_7:0
C9hCOMP_THRESHOLD_HI_CHA_11:8
CAhCOMP_THRESHOLD_HI_CHB_7:0
CBhCOMP_THRESHOLD_HI_CHB_11:8
CChCOMP_THRESHOLD_LO_CHA_7:0
CDhCOMP_THRESHOLD_LO_CHA_11:8
CEhCOMP_THRESHOLD_LO_CHB_7:0
CFhCOMP_THRESHOLD_LO_CHB_11:8
D0hCOMP_HYSTERESIS_CHA_7:0
D1hCOMP_HYSTERESIS_CHA_11:8
D2hCOMP_HYSTERISIS_CHB_7:0
D3hCOMP_HYSTERISIS_CHB_11:8
D3hCOMP_SLEW
D4hDECIMATION
D5hPROG_GAIN_CHA
D6hPROG_GAIN_CHB
D8hIL_GAIN_CHA_7:0
D9hIL_GAIN_CHA_15:8
DAhIL_GAIN_CHB_7:0
DBhIL_GAIN_CHB_15:8
DChOFFSET_CHA_7:0
DDhOFFSET_CHA_15:8
DEhOFFSET_CHB_7:0
DFhOFFSET_CHB_15:8
E0hCH_CORR_EN
200hDDC_CFG_1
201hSTATS_COMP_DATA_SEL
202hOUTPUT_DATA_SEL
203hCOMP_DDC_DATA_SEL
204hOUTPUT_STATS_DATA_SEL
205hOVR_CHB
206hOVR_CHA
304hCLK_TIM_ADJ_CHA
305hCLK_TIM_ADJ_CHB
306hDCLK_DLL_PD
307hDIG_INPUT_CFG
309hBUF_VCM_CURR
30AhBUF_CURR
30BhDEV_CFG_4
484hGBL_CLK_CFG_1
4BEhGBL_CLK_CFG_2
4BFhGBL_CLK_CFG_3

Complex bit access types are encoded to fit into small table cells. Table 6-6 shows the codes that are used for access types in this section.

Table 6-6 Device Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.1.1 RESET Register (Address = 0h) [Reset = 00h]

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Table 6-7 RESET Register Field Descriptions
BitFieldTypeResetDescription
7RESETW0h This bit resets all internal registers to the default values and self clears to 0.
6:0RESERVEDR0h

6.6.1.2 CFG_ALERT Register (Address = 38h) [Reset = 0h]

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Table 6-8 CFG_ALERT Register Field Descriptions
BitFieldTypeResetDescription
0CFG_ALERTR0h Indicates that the device is ready to be configured. The user can poll this bit before starting the device configuration. Alternatively, the user can wait for a fixed time (2000 clock cycles) after reset release before triggering device configuration

6.6.1.3 SPARE_REG Register (Address = 39h) [Reset = 00h]

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Table 6-9 SPARE_REG Register Field Descriptions
BitFieldTypeResetDescription
7:0SPARE_REGR/W0h This field has no functionality and can be used for validating SPI writes.

6.6.1.4 INTERLEAVE Register (Address = 84h) [Reset = 0h]

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Table 6-10 INTERLEAVE Register Field Descriptions
BitFieldTypeResetDescription
2INTERLEAVER/W0h Enables interleaving mode where channels A and B are both sampling channel A input and channel B clock is 180 degrees out of phase with respect to channel A to achieve a 2x sampling rate. Only applies to dual channel devices.
0b = Interleaving mode disabled
1b = Interleaving mode enabled
1:0RESERVEDR0h

6.6.1.5 REF_EQ Register (Address = 85h) [Reset = 00h]

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Table 6-11 REF_EQ Register Field Descriptions
BitFieldTypeResetDescription
6REF_EQR/W0h Enable when using external reference to improve temperature tracking. Internal bandgap is expected to have 7 mV of variation across the device operating temperature.
0b = Reference equalization disabled
1b = Reference equalization enabled
5:0RESERVEDR0h

6.6.1.6 CLK_RESET Register (Address = 87h) [Reset = 00h]

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Table 6-12 CLK_RESET Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR0h Reserved
6RESERVEDR0h Reserved
5:0RESERVEDR0h

6.6.1.7 DEV_CFG_1 Register (Address = 88h) [Reset = 00h]

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Table 6-13 DEV_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
7FCLK_ENR/W0h Enables frame clock output on DCLKZ pin. Must be enabled in Serial CMOS mode.
0b = Frame clock output on DCLKZ pin disabled
1b = Frame clock output on DCLKZ pin enabled
6CNL_PDNR/W0h Powers down internal non-linearity correction. Useful for input frequencies above 100 MHz and reduces current by 0.5 mA.
0b = Non-linearity correction enabled
1b = Non-linearity correction powered down
5BUF_CHBR/W0h Reduces current to ADC channel B input buffer which reduces buffer bandwidth. Recommended for input signals below 25 MHz and reduces current consumption by 2 mA.
0b = Input buffer full power mode
1b = Input buffer low power mode
4BUF_CHAR/W0h Reduces current to ADC channel A input buffer which reduces buffer bandwidth. Recommended for input signals below 25 MHz. Reduces current consumption by 2 mA.
0b = Input buffer full power mode
1b = Input buffer low power mode
3:0RESERVEDR0h

6.6.1.8 DEV_CFG_2 Register (Address = 89h) [Reset = 00h]

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Table 6-14 DEV_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
7DCLK_FL_DLY__0R/W0h Adjust the delay on the falling edge of DCLK where T is the period of DCLK.
0b = No adjustment
1b = T/20 (T/10 with HFSB = 1)
1010b = -T/10 (-T/5 with HFSB = 1)
1011b = -T/20 (-T/10 with HFSB = 1)
6DIG_DCLKR/W0h By default CLK is DCLK for digital blocks. Enable when CLK and DCLK are different and DCLKIN is used.
0b = CLK used as DCLK for digital blocks
1b = DCLKIN used as DCLK for digital blocks
5DIG_DATAR/W0h Data from digital block used as output data.
0b = Digital data to output data disabled
1b = Digital data to output data enabled
4:0RESERVEDR0h

6.6.1.9 CLK_CFG_1 Register (Address = 8Ah) [Reset = 00h]

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Table 6-15 CLK_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
5DIG_CLK_SELR/W0h By default CLK is DCLK for digital blocks. Enable when CLK and DCLK are different and DCLKIN is used.
0b = CLK used as CLK for digital blocks
1b = Relatched CLK using DCLKIN used as CLK for digital blocks
4RESERVEDR0h
3CHB_CLKR/W0h Enable when only ADC channel A is disabled, ADC channel B is enabled and HDDR interface mode is used.
2:1DCLK_RISE_DLYR/W0h Adjust the delay on the rising edge of DCLK where T is the period of DCLK.
00b = No adjustment
01b = T/20 (T/10 with HFSB = 1)
10b = -T/10 (-T/5 with HFSB = 1)
11b = -T/20 (-T/10 with HFSB = 1)
0DCLK_FL_DLY__1R/W0h Adjust the delay on the falling edge of DCLK where T is the period of DCLK.
0b = No adjustment
1b = T/20 (T/10 with HFSB = 1)
10b = -T/10 (-T/5 with HFSB = 1)
11b = -T/20 (-T/10 with HFSB = 1)

6.6.1.10 CLK_CFG_2 Register (Address = 8Bh) [Reset = 00h]

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Table 6-16 CLK_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
5:4DCLKZ_RISE_DLYR/W0h Adjust the delay on the rising edge of DCLKZ where T is the period of DCLK.
00b = No adjustment
01b = T/20 (T/10 with HFSB = 1)
10b = -T/10 (-T/5 with HFSB = 1)
11b = -T/20 (-T/10 with HFSB = 1)
3RESERVEDR0h
2:1DCLKZ_FALL_DLYR/W0h Adjust the delay on the falling edge of DCLKZ where T is the period of DCLK.
00b = No adjustment
01b = T/20 (T/10 with HFSB = 1)
10b = -T/10 (-T/5 with HFSB = 1)
11b = -T/20 (-T/10 with HFSB = 1)
0RESERVEDR0h

6.6.1.11 PDN_CFG Register (Address = 8Ch) [Reset = 00h]

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Table 6-17 PDN_CFG Register Field Descriptions
BitFieldTypeResetDescription
7CHA_PDNR/W0h Powers down ADC channel A. Reduces current by 12 mA.
0b = ADC channel A enabled
1b = ADC channel A powered down
6CHB_PDNR/W0h Powers down ADC channel B. Reduces current by 12 mA.
0b = ADC channel B enabled
1b = ADC channel B powered down
5MASK_REFR/W0h Fast power down mask control for reference amplifier.
0b = Reference amplifier powered down when fast power down is exercised.
1b = Reference amplifier NOT powered down when fast power down is exercised.
4MASK_VCMR/W0h Fast power down mask control for VCM buffer.
0b = VCM buffer powered down when fast power down is exercised.
1b = Reference amplifier NOT powered down when fast power down is exercised.
3MASK_DLLR/W0h Fast power down mask control for CLK DLL and DCLK DLL.
0b = DLLs powered down when fast power down is exercised.
1b = DLLs NOT powered down when fast power down is exercised.
2SDR_CHB_SELR/W0h Selects the channel data to be sent out in SDR interface mode. Enable SDR with Channel B output when asserted.
0b = Channel A data
1b = Channel B data
1:0RESERVEDR0h

6.6.1.12 DEV_CFG_3 Register (Address = 8Dh) [Reset = 00h]

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Table 6-18 DEV_CFG_3 Register Field Descriptions
BitFieldTypeResetDescription
6FORMATR/W0h Output Data Format when digital features are bypassed.
0b = Two's Complement
1b = Offset binary
5:4RESERVEDR0h
3DCLKZ_DLLR/W0h Swap DCLKZ_OUT to DCLK output of DLL
0b = DCLKZ_OUT to DCLKZ output of DLL
1b = DCLKZ_OUT to DCLK output of DLL
2DCLK_DLLR/W0h Swap DCLK_OUT to DCLKZ output of DLL
0b = DCLK_OUT to DCLK output of DLL
1b = DCLK_OUT to DCLKZ output of DLL
1ALERT_POLR/W0h ALERT pin polarity
0b = ALERT pin active high
1b = ALERT pin active low
0RESERVEDR0h

6.6.1.13 CLK_CFG_3 Register (Address = 8Eh) [Reset = 00h]

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Table 6-19 CLK_CFG_3 Register Field Descriptions
BitFieldTypeResetDescription
7:6DCLK_SYNCR/W0h Used for DDR and SDR interface modes
00b = DDR Clocking mode (DCLKZ is inversion of DCLK)
01b = DDR Clocking
1010b = SDR Clocking (DCLKZ is same as DCLK)
1011b = DCLK/DCLKZ off
5:2RESERVEDR0h
1ADLL_BYPR/W0h Bypass analog DLL. Enable this setting when ADC clock frequency below 25MHz. Reduces current by 1mA.
0b = Normal operation
1b = Analog DLL bypassed
0RESERVEDR0h

6.6.1.14 CLK_CFG_4 Register (Address = 8Fh) [Reset = 00h]

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Table 6-20 CLK_CFG_4 Register Field Descriptions
BitFieldTypeResetDescription
6RESERVEDR0h Reserved
5RESERVEDR0h Reserved
4DCLK_DLLR/W0h Enable when digital features are used
3:0RESERVEDR0h

6.6.1.15 PIN_CFG_1 Register (Address = 90h) [Reset = 00h]

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Table 6-21 PIN_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
7ALERT_ODR/W0h Alert output pin mode
0b = Push-pull
1b = Open-drain
6:4RESERVEDR0h
3:1CLK_PIN_STRENGTHR/W0h DCLK and DCLKZ output pin strength
000b = 15/15 (default)
001b = 13/15
010b = 11/15
011b = 9/15
100b = 7/15
101b = 5/15
110b = 3/15
111b = 1/15
0RESERVEDR0h

6.6.1.16 TEST_PAT_CFG Register (Address = 91h) [Reset = 0h]

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Table 6-22 TEST_PAT_CFG Register Field Descriptions
BitFieldTypeResetDescription
3:0DATA_PIN_STRENGTHR/W0h D11 to D0 output pin strength
0000b = 15/15 (default)
0001b = 14/15
0010b = 13/15
0011b = 12/15
0100b = 11/15
0101b = 10/15
0110b = 9/15
0111b = 8/15
1000b = 7/15
1001b = 6/15
1010b = 5/15
1011b = 4/15
1100b = 3/15
1101b = 2/15
1110b = 1/15
1111b = 0/15 (Tri-state)

6.6.1.17 TEST_PATTERN_CFG Register (Address = 91h) [Reset = 00h]

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Table 6-23 TEST_PATTERN_CFG Register Field Descriptions
BitFieldTypeResetDescription
6TOGGLE_PATR/W0h Toggle mode for test pattern. Enable to toggle all lanes in SDR mode, disable in DDR mode.
0b = Disable test pattern toggle
1b = Enable test pattern toggle
5TEST_PAT_BR/W0h Enables the test pattern in register 0x0092
0b = Channel B test pattern disabled
1b = Channel B test pattern enabled
4TEST_PAT_AR/W0h Enables the test pattern in register 0x0094
0b = Channel A test pattern disabled
1b = Channel A test pattern enabled
3:0RESERVEDR0h

6.6.1.18 TEST_PATTERN_CHB_7:0 Register (Address = 92h) [Reset = 00h]

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Table 6-24 TEST_PATTERN_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0TEST_PATTERN_CHB__7:0R/W0h

6.6.1.19 TEST_PATTERN_CHB_13:8 Register (Address = 93h) [Reset = 00h]

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Table 6-25 TEST_PATTERN_CHB_13:8 Register Field Descriptions
BitFieldTypeResetDescription
5:0TEST_PATTERN_CHB__13:8R/W0h

6.6.1.20 TEST_PATTERN_CHA_7:0 Register (Address = 94h) [Reset = 00h]

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Table 6-26 TEST_PATTERN_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0TEST_PATTERN_CHA__7:0R/W0h

6.6.1.21 TEST_PATTERN_CHA_13:8 Register (Address = 95h) [Reset = 00h]

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Table 6-27 TEST_PATTERN_CHA_13:8 Register Field Descriptions
BitFieldTypeResetDescription
5:0TEST_PATTERN_CHA__13:8R/W0h

6.6.1.22 GLOBAL_PDN Register (Address = 97h) [Reset = 00h]

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Table 6-28 GLOBAL_PDN Register Field Descriptions
BitFieldTypeResetDescription
5PDNR/W0h Global power down via SPI.
0b = Global power down disabled
1b = Global power down enabled.
4:0RESERVEDR0h

6.6.1.23 INTERFACE_CFG_1 Register (Address = 98h) [Reset = 00h]

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Table 6-29 INTERFACE_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
7OENZ_PDNR/W0h Overwrites OENZ control pin as either global or fast power down
0b = OENZ control pin functions as output enable
1b = OENZ control pin functions as power down. Power down options in register 0x009C determine the power down mode.
6RESERVEDR0h
5HDDR_ENR/W0h Enable HDDR interface mode
0b = HDDR interface mode disabled
1b = HDDR interface mode enabled
4SDR_ENR/W0h Enable SDR interface mode
0b = SDR interface mode disabled
1b = SDR interface mode enabled
3:0ALERT_PIN_STRENGTHR/W0h ALERT output pin strength
0000b = 15/15 (default)
0001b = 14/15
0010b = 13/15
0011b = 12/15
0100b = 11/15
0101b = 10/15
0110b = 9/15
0111b = 8/15
1000b = 7/15
1001b = 6/15
1010b = 5/15
1011b = 4/15
1100b = 3/15
1101b = 2/15
1110b = 1/15
1111b = 0/15 (Tri-state)

6.6.1.24 INTERFACE_CFG_2 Register (Address = 9Ch) [Reset = 00h]

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Table 6-30 INTERFACE_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
6OENZ_GPDNR/W0h Overwrites OENZ control pin as global power down. Global power down superseeds fast power down.
0b = OENZ control pin functions as output enable
1b = OENZ control pin functions as global power down
5OENZ_FPDNR/W0h Overwrites OENZ control pin as fast power down. Global power down superseeds fast power down.
0b = OENZ control pin functions as output enable
1b = OENZ control pin functions as fast power down
4:2RESERVEDR0h
1:0ALERT_PIN_SELR/W0h Alert output pin function. By default the ALERT output pin monitors overranging at the ADC core.
00b = Channel A overrange (OVR CHA) || Channel B overrange (OVR CHB)
01b = Channel A overrange (OVR CHA)
10b = Channel B overrange (OVR CHB)
11b = Digital Alerts

6.6.1.25 HFSB_FPDN_CFG Register (Address = 9Eh) [Reset = 00h]

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Table 6-31 HFSB_FPDN_CFG Register Field Descriptions
BitFieldTypeResetDescription
6:5HFSB_CONFIGR/W0h DCLK generation block control. Used when global HFSB is 0 (CLK is greater than 65 MSPS) and DCLK is less than 65 MSPS, e.g. decimation. Forces half speed mode on DCLK generation block.
00b = Half speed mode for DCLK disabled
11b = Half speed mode for DCLK enabled
4PDN_FASTR/W0h Fast power down via SPI.
0b = Fast power down disabled
1b = Fast power down enabled. Power down mask (register 0x008C) determines which internal blocks are powered down.
3:0RESERVEDR0h

6.6.1.26 INTERFACE_CFG_3 Register (Address = A0h) [Reset = 00h]

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Table 6-32 INTERFACE_CFG_3 Register Field Descriptions
BitFieldTypeResetDescription
5CHB_SWAPR/W0h Selects the channel data to send on Channel B output. Applicable in DDR interface mode and only available when digital enabled.
0b = Channel B data on channel B output
1b = Channel A data on channel B output
4CHA_SWAPR/W0h Selects the channel data to send on Channel A output. Applicable in DDR interface mode and only available when digital enabled.
0b = Channel A data on channel A output
1b = Channel B data on channel A output
3OENZ_PIN_VALR/W0h Value to be overwritten on OENZ pin. Must enable OENZ overwrite in register 0x00A0, bit 2.
2OENZ_PIN_OWR/W0h OENZ pin overwrite
0b = Use value on OENZ pin
1b = Use value from OENZ_PIN_ VAL. Ignore value on OENZ pin.
1:0RESERVEDR0h

6.6.1.27 DIG_PATTERN_EN Register (Address = A1h) [Reset = 00h]

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Table 6-33 DIG_PATTERN_EN Register Field Descriptions
BitFieldTypeResetDescription
5:3DIG_PATTERN_MODE_CHBR/W0h Enables test pattern output mode for channel B.
001b = Ramp pattern with step size of 1
010b = Ramp pattern with step size set in DIG PAT CHA
100b = Constant pattern using DIG PAT CHA
101b = Toggle pattern between DIG PAT CHA and bitwise inverted DIG PAT CHA
110b = Toggle pattern between DIG PAT CHA and 0
2:0DIG_PATTERN_MODE_CHAR/W0h Enables test pattern output mode for channel A.
001b = Ramp pattern with step size of 1
010b = Ramp pattern with step size set in DIG PAT CHA
100b = Constant pattern using DIG PAT CHA
101b = Toggle pattern between DIG PAT CHA and bitwise inverted DIG PAT CHA
110b = Toggle pattern between DIG PAT CHA and 0

6.6.1.28 DIG_PATTERN_CHA_7:0 Register (Address = A2h) [Reset = 00h]

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Table 6-34 DIG_PATTERN_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0DIG_PATTERN_CHA__7:0R/W0h Used with DIG PAT MODE CHA to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.29 DIG_PATTERN_CHA_15:8 Register (Address = A3h) [Reset = 00h]

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Table 6-35 DIG_PATTERN_CHA_15:8 Register Field Descriptions
BitFieldTypeResetDescription
7:0DIG_PATTERN_CHA__15:8R/W0h Used with DIG PAT MODE CHA to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.30 DIG_PATTERN_CHB_7:0 Register (Address = A4h) [Reset = 00h]

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Table 6-36 DIG_PATTERN_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0DIG_PATTERN_CHB__7:0R/W0h Used with DIG PAT MODE CHB to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.31 DIG_PATTERN_CHB_15:8 Register (Address = A5h) [Reset = 00h]

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Table 6-37 DIG_PATTERN_CHB_15:8 Register Field Descriptions
BitFieldTypeResetDescription
7:0DIG_PATTERN_CHB__15:8R/W0h Used with DIG PAT MODE CHB to set constant custom pattern starting from MSB or sets ramp pattern increment step size.

6.6.1.32 INTERFACE_CFG_4 Register (Address = A6h) [Reset = 00h]

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Table 6-38 INTERFACE_CFG_4 Register Field Descriptions
BitFieldTypeResetDescription
5DDR_MODER/W0h Channel data output order. Applicable in DDR interface mode.
0b = Channel A data on rising edge and channel B on falling edge of DCLK
1b = Channel A data outputed first then channel B data
4:1SERIALIZATIONR/W0h Serialization Factor
0000b = Parellel output
0001b = 2x serialization
0010b = 4x serialization
0011b = 8x serialization
0100b = 16x serialization
0DIG_PAT_ENR/W0h Enables the test patterns set in DIG PAT MODE CHA and DIG PAT MODE CHB.
0b = Normal output mode (test pattern disabled)
1b = Test pattern enabled

6.6.1.33 OUTPUT_DATA_WIDTH Register (Address = A7h) [Reset = 50h]

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Table 6-39 OUTPUT_DATA_WIDTH Register Field Descriptions
BitFieldTypeResetDescription
4:0OUTPUT_DATA_WIDTHR/WAh Output resolution for lane optimization in serialization modes.
01000b = 8-bit
01010b = 10-bit
01100b = 12-bit
10000b = 16-bit

6.6.1.34 DCLK_DIVIDER Register (Address = A8h) [Reset = 0h]

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Table 6-40 DCLK_DIVIDER Register Field Descriptions
BitFieldTypeResetDescription
3:0DCLK_DIVIDERR/W0h Division of CLK to DCLK to match serialization and decimation data rates. Decimation and serialization factor (SERIALIZATION) must match.
0000b = Divide-by-1
0001b = Divide-by-2
0011b = Divide-by-4
0111b = Divide-by-8
1111b = Divide-by-16

6.6.1.35 OUTPUT_BIT_MAPPER_D0_D1 Register (Address = AEh) [Reset = D6h]

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Table 6-41 OUTPUT_BIT_MAPPER_D0_D1 Register Field Descriptions
BitFieldTypeResetDescription
7:4OUTPUT_BIT_MAPPER_D1R/WDh These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)
3:0OUTPUT_BIT_MAPPER_D0R/W6h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)

6.6.1.36 OUTPUT_BIT_MAPPER_D2_D3 Register (Address = AFh) [Reset = EBh]

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Table 6-42 OUTPUT_BIT_MAPPER_D2_D3 Register Field Descriptions
BitFieldTypeResetDescription
7:4OUTPUT_BIT_MAPPER_D3R/WEh These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)
3:0OUTPUT_BIT_MAPPER_D2R/WBh These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)

6.6.1.37 OUTPUT_BIT_MAPPER_D4_D5 Register (Address = B0h) [Reset = 84h]

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Table 6-43 OUTPUT_BIT_MAPPER_D4_D5 Register Field Descriptions
BitFieldTypeResetDescription
7:4OUTPUT_BIT_MAPPER_D5R/W8h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)
3:0OUTPUT_BIT_MAPPER_D4R/W4h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)

6.6.1.38 OUTPUT_BIT_MAPPER_D6_D7 Register (Address = B1h) [Reset = 86h]

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Table 6-44 OUTPUT_BIT_MAPPER_D6_D7 Register Field Descriptions
BitFieldTypeResetDescription
7:4OUTPUT_BIT_MAPPER_D7R/W8h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)
3:0OUTPUT_BIT_MAPPER_D6R/W6h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)

6.6.1.39 OUTPUT_BIT_MAPPER_D8_D9 Register (Address = B2h) [Reset = 92h]

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Table 6-45 OUTPUT_BIT_MAPPER_D8_D9 Register Field Descriptions
BitFieldTypeResetDescription
7:4OUTPUT_BIT_MAPPER_D9R/W9h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)
3:0OUTPUT_BIT_MAPPER_D8R/W2h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)

6.6.1.40 OUTPUT_BIT_MAPPER_D10_D11 Register (Address = B3h) [Reset = 93h]

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Table 6-46 OUTPUT_BIT_MAPPER_D10_D11 Register Field Descriptions
BitFieldTypeResetDescription
7:4OUTPUT_BIT_MAPPER_D11R/W9h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)
3:0OUTPUT_BIT_MAPPER_D10R/W3h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program.
0100b = Lane 0 (LSB)
0101b = Lane 1
0110b = Lane 2
0111b = Lane 3
1000b = Lane 4
1001b = Lane 5
1010b = Lane 6
1011b = Lane 7
1100b = Lane 8
1101b = Lane 9
1110b = Lane 10
1111b = Lane 11 (MSB)

6.6.1.41 ROUND Register (Address = B6h) [Reset = 00h]

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Table 6-47 ROUND Register Field Descriptions
BitFieldTypeResetDescription
4ROUNDR/W0h The device uses a 16-bit resolution internally which can be useful for high decimation settings so that the quantization noise doesn't impact the ADC performance.
0b = Truncate 4 LSBs to reduce resolution from 16 bits to resolution specified in OUTPUT DATA WIDTH
1b = Round to reduce resolution from 16 bits to resolution specified in OUTPUT DATA WIDTH
3:0RESERVEDR0h

6.6.1.42 COMP_THRESHOLD_HI_CHA_7:0 Register (Address = C8h) [Reset = 00h]

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Table 6-48 COMP_THRESHOLD_HI_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0COMP_THRESHOLD_HI_CHA__7:0R/W0h Comparator high threshold for channel A

6.6.1.43 COMP_THRESHOLD_HI_CHA_11:8 Register (Address = C9h) [Reset = 0h]

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Table 6-49 COMP_THRESHOLD_HI_CHA_11:8 Register Field Descriptions
BitFieldTypeResetDescription
3:0COMP_THRESHOLD_HI_CHA__11:8R/W0h Comparator high threshold for channel A

6.6.1.44 COMP_THRESHOLD_HI_CHB_7:0 Register (Address = CAh) [Reset = 00h]

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Table 6-50 COMP_THRESHOLD_HI_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0COMP_THRESHOLD_HI_CHB__7:0R/W0h Comparator high threshold for channel B

6.6.1.45 COMP_THRESHOLD_HI_CHB_11:8 Register (Address = CBh) [Reset = 0h]

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Table 6-51 COMP_THRESHOLD_HI_CHB_11:8 Register Field Descriptions
BitFieldTypeResetDescription
3:0COMP_THRESHOLD_HI_CHB__11:8R/W0h Comparator high threshold for channel B

6.6.1.46 COMP_THRESHOLD_LO_CHA_7:0 Register (Address = CCh) [Reset = 00h]

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Table 6-52 COMP_THRESHOLD_LO_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0COMP_THRESHOLD_LO_CHA__7:0R/W0h Comparator low threshold for channel A

6.6.1.47 COMP_THRESHOLD_LO_CHA_11:8 Register (Address = CDh) [Reset = 0h]

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Table 6-53 COMP_THRESHOLD_LO_CHA_11:8 Register Field Descriptions
BitFieldTypeResetDescription
3:0COMP_THRESHOLD_LO_CHA__11:8R/W0h Comparator low threshold for channel A

6.6.1.48 COMP_THRESHOLD_LO_CHB_7:0 Register (Address = CEh) [Reset = 00h]

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Table 6-54 COMP_THRESHOLD_LO_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0COMP_THRESHOLD_LO_CHB__7:0R/W0h Comparator low threshold for channel B

6.6.1.49 COMP_THRESHOLD_LO_CHB_11:8 Register (Address = CFh) [Reset = 0h]

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Table 6-55 COMP_THRESHOLD_LO_CHB_11:8 Register Field Descriptions
BitFieldTypeResetDescription
3:0COMP_THRESHOLD_LO_CHB__11:8R/W0h Comparator low threshold for channel B

6.6.1.50 COMP_HYSTERESIS_CHA_7:0 Register (Address = D0h) [Reset = 00h]

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Table 6-56 COMP_HYSTERESIS_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0COMP_HYSTERESIS_CHA__7:0R/W0h Comparator hysteresis for channel A

6.6.1.51 COMP_HYSTERESIS_CHA_11:8 Register (Address = D1h) [Reset = 0h]

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Table 6-57 COMP_HYSTERESIS_CHA_11:8 Register Field Descriptions
BitFieldTypeResetDescription
3:0COMP_HYSTERESIS_CHA__11:8R/W0h Comparator hysteresis for channel A

6.6.1.52 COMP_HYSTERISIS_CHB_7:0 Register (Address = D2h) [Reset = 00h]

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Table 6-58 COMP_HYSTERISIS_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0COMP_HYSTERISIS_CHB__7:0R/W0h Comparator hysteresis for channel A

6.6.1.53 COMP_HYSTERISIS_CHB_11:8 Register (Address = D3h) [Reset = 0h]

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Table 6-59 COMP_HYSTERISIS_CHB_11:8 Register Field Descriptions
BitFieldTypeResetDescription
3:0COMP_HYSTERISIS_CHB__11:8R/W0h Comparator hysteresis for channel A

6.6.1.54 COMP_SLEW Register (Address = D3h) [Reset = 00h]

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Table 6-60 COMP_SLEW Register Field Descriptions
BitFieldTypeResetDescription
5SLEW_CHBR/W0h Comparison method for channel B
0b = Standard compare (THRESHOLD HI CHB - HYSTERESIS CHB, THRESHOLD LO CHB + HYSTERESIS CHB)
1b = Slew compare (current sample - previous sample > THRESHOLD HI CHB, current sample - previous sample < THRESHOLD LO CHB) HYSTERESIS CHB must be set to 0.
4SLEW_CHAR/W0h Comparison method for channel A
0b = Standard compare (THRESHOLD HI CHA - HYSTERESIS CHA, THRESHOLD LO CHA + HYSTERESIS CHA)
1b = Slew compare (current sample - previous sample > THRESHOLD HI CHA, current sample - previous sample < THRESHOLD LO CHA) HYSTERESIS CHA must be set to 0.
3:0RESERVEDR0h

6.6.1.55 DECIMATION Register (Address = D4h) [Reset = 0h]

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Table 6-61 DECIMATION Register Field Descriptions
BitFieldTypeResetDescription
3DDC_CHBR/W0h Channel B decimation
0b = Decimation disabled
1b = Decimation enabled
2DDC_CHAR/W0h Channel A decimation
0b = Decimation disabled
1b = Decimation enabled
1:0RESERVEDR0h

6.6.1.56 PROG_GAIN_CHA Register (Address = D5h) [Reset = 00h]

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Table 6-62 PROG_GAIN_CHA Register Field Descriptions
BitFieldTypeResetDescription
7:0PROG_GAIN_CHAR/W0h Programmable gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15.

6.6.1.57 PROG_GAIN_CHB Register (Address = D6h) [Reset = 00h]

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Table 6-63 PROG_GAIN_CHB Register Field Descriptions
BitFieldTypeResetDescription
7:0PROG_GAIN_CHBR/W0h Programmable gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15

6.6.1.58 IL_GAIN_CHA_7:0 Register (Address = D8h) [Reset = 00h]

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Table 6-64 IL_GAIN_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0IL_GAIN_CHA__7:0R/W0h Interleaving gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15

6.6.1.59 IL_GAIN_CHA_15:8 Register (Address = D9h) [Reset = 00h]

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Table 6-65 IL_GAIN_CHA_15:8 Register Field Descriptions
BitFieldTypeResetDescription
7:0IL_GAIN_CHA__15:8R/W0h Interleaving gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15

6.6.1.60 IL_GAIN_CHB_7:0 Register (Address = DAh) [Reset = 00h]

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Table 6-66 IL_GAIN_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0IL_GAIN_CHB__7:0R/W0h Interleaving gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15

6.6.1.61 IL_GAIN_CHB_15:8 Register (Address = DBh) [Reset = 00h]

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Table 6-67 IL_GAIN_CHB_15:8 Register Field Descriptions
BitFieldTypeResetDescription
7:0IL_GAIN_CHB__15:8R/W0h Interleaving gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15

6.6.1.62 OFFSET_CHA_7:0 Register (Address = DCh) [Reset = 00h]

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Table 6-68 OFFSET_CHA_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0OFFSET_CHA__7:0R/W0h Channel A offset. Effective offset = OFFSET CHA/2**15

6.6.1.63 OFFSET_CHA_15:8 Register (Address = DDh) [Reset = 00h]

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Table 6-69 OFFSET_CHA_15:8 Register Field Descriptions
BitFieldTypeResetDescription
7:0OFFSET_CHA__15:8R/W0h Channel A offset. Effective offset = OFFSET CHA/2**15

6.6.1.64 OFFSET_CHB_7:0 Register (Address = DEh) [Reset = 00h]

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Table 6-70 OFFSET_CHB_7:0 Register Field Descriptions
BitFieldTypeResetDescription
7:0OFFSET_CHB__7:0R/W0h Channel B offset. Effective offset = OFFSET CHB/2**15

6.6.1.65 OFFSET_CHB_15:8 Register (Address = DFh) [Reset = 00h]

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Table 6-71 OFFSET_CHB_15:8 Register Field Descriptions
BitFieldTypeResetDescription
7:0OFFSET_CHB__15:8R/W0h Channel B offset. Effective offset = OFFSET CHB/2**15

6.6.1.66 CH_CORR_EN Register (Address = E0h) [Reset = 3h]

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Table 6-72 CH_CORR_EN Register Field Descriptions
BitFieldTypeResetDescription
1CORR_CHB__15:8R/W1h Channel corrections for channel B (PROG GAIN CHB, IL GAIN CHB, OFFSET CHB)
0b = Channel corrections enabled
1b = Channel corrections disabled
0CORR_CHA__7:0R/W1h Channel corrections for channel A (PROG GAIN CHA, IL GAIN CHA, OFFSET CHA)
0b = Channel corrections enabled
1b = Channel corrections disabled

6.6.1.67 DDC_CFG_1 Register (Address = 200h) [Reset = 00h]

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Table 6-73 DDC_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
5:3DDC_DATA_SEL_CHAR/W0h Data select for channel A decimation
000b = ADC channel A (default)
001b = ADC channel B
2:0DECIMATIONR/W0h Real decimation setting. This applies to both channels.
000b = Bypass mode (no decimation)
001b = Decimation by 2
010b = Decimation by 4
011b = Decimation by 8
100b = Decimation by 16

6.6.1.68 STATS_COMP_DATA_SEL Register (Address = 201h) [Reset = 00h]

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Table 6-74 STATS_COMP_DATA_SEL Register Field Descriptions
BitFieldTypeResetDescription
5:3STATS_DATA_SEL_CHAR/W0h Data select for channel A statistics engine
000b = Channel A digital downconverter
001b = ADC channel B
100b = Average of channel A and channel B data
101b = Channel A correction block
110b = Channel B correction block
2:0COMP_DATA_SEL_CHAR/W0h Data select for channel A comparator
000b = Channel A digital downconverter
001b = ADC channel B
100b = Average of channel A and channel B data
101b = Channel A correction block
110b = Channel B correction block

6.6.1.69 OUTPUT_DATA_SEL Register (Address = 202h) [Reset = 0h]

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Table 6-75 OUTPUT_DATA_SEL Register Field Descriptions
BitFieldTypeResetDescription
2:0OUTPUT_DATA_SEL_CHAR/W0h Data select for channel A output
000b = Channel A digital downconverter
001b = ADC channel B
100b = Average of channel A and channel B data
101b = Channel A correction block
110b = Channel B correction block

6.6.1.70 COMP_DDC_DATA_SEL Register (Address = 203h) [Reset = 21h]

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Table 6-76 COMP_DDC_DATA_SEL Register Field Descriptions
BitFieldTypeResetDescription
5:3COMP_DATA_SEL_CHBR/W1h Data select for channel B comparator
000b = Channel A digital downconverter
001b = ADC channel B (default)
100b = Average of channel A and channel B data
101b = Channel A correction block
110b = Channel B correction block
2:0DDC_DATA_SEL_CHBR/W1h Data select for channel B decimation
000b = ADC channel A
001b = ADC channel B (default)

6.6.1.71 OUTPUT_STATS_DATA_SEL Register (Address = 204h) [Reset = 21h]

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Table 6-77 OUTPUT_STATS_DATA_SEL Register Field Descriptions
BitFieldTypeResetDescription
5:3OUTPUT_DATA_SEL_CHBR/W1h Data select for channel B output
000b = Channel A digital downconverter
001b = ADC channel B (default)
100b = Average of channel A and channel B data
101b = Channel A correction block
110b = Channel B correction block
2:0STATS_DATA_SEL_CHBR/W1h Data select for channel B statistics engine
000b = Channel A digital downconverter
001b = ADC channel B (default)
100b = Average of channel A and channel B data
101b = Channel A correction block
110b = Channel B correction block

6.6.1.72 OVR_CHB Register (Address = 205h) [Reset = F0h]

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Table 6-78 OVR_CHB Register Field Descriptions
BitFieldTypeResetDescription
6:3OVR_CHBR/WFh Channel B overrange control. This register is a mask with all sources enabled by default. Bit 0: Truncation overrange Bit 1: Channel Correction overrange Bit 2: Decimation overrange Bit 3: ADC overrange
2:0RESERVEDR0h

6.6.1.73 OVR_CHA Register (Address = 206h) [Reset = Fh]

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Table 6-79 OVR_CHA Register Field Descriptions
BitFieldTypeResetDescription
3:0OVR_CHARFh Channel A overrange control. This register is a mask with all sources enabled by default. Bit 0: Truncation overrange Bit 1: Channel Correction overrange Bit 2: Decimation overrange Bit 3: ADC overrange

6.6.1.74 CLK_TIM_ADJ_CHA Register (Address = 304h) [Reset = 00h]

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Table 6-80 CLK_TIM_ADJ_CHA Register Field Descriptions
BitFieldTypeResetDescription
7:1CLK_TIM_ADJ_CHAR/W0h ADC channel A sampling edge adjustment. Used in interleaved mode to reduce interleaving spur. Min. step size is 1 ps and adjustment range is 15 ps.
0RESERVEDR0h

6.6.1.75 CLK_TIM_ADJ_CHB Register (Address = 305h) [Reset = 00h]

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Table 6-81 CLK_TIM_ADJ_CHB Register Field Descriptions
BitFieldTypeResetDescription
7DCLK_OUTR/W0h DCLK output disable
0b = DCLK output enabled
1b = DCLK output disabled
6:0CLK_TIM_ADJ_CHBR/W0h ADC channel B sampling edge adjustment. Used in interleaved mode to reduce interleaving spur. Min. step size is 1 ps and adjustment range is 15 ps.

6.6.1.76 DCLK_DLL_PD Register (Address = 306h) [Reset = 0h]

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Table 6-82 DCLK_DLL_PD Register Field Descriptions
BitFieldTypeResetDescription
0DCLKDLL_PDR/W0h DCLK DLL power down and bypass. Useful in SDR interface mode and reduces current by 1 mA.
0b = DCLK DLL enabled
1b = DCLK DLL power down and bypassed

6.6.1.77 DIG_INPUT_CFG Register (Address = 307h) [Reset = 00h]

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Table 6-83 DIG_INPUT_CFG Register Field Descriptions
BitFieldTypeResetDescription
4DCLKZ_OUTR/W0h DCLKZ output disable
0b = DCLKZ output enabled
1b = DCLKZ output disabled
3DIG_INPUTR/W0h Disables data inputs to digital block.
0b = Data inputs enabled to digital blocks
1b = Data input disabled to digital blocks
2:0RESERVEDR0h

6.6.1.78 BUF_VCM_CURR Register (Address = 309h) [Reset = 00h]

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Table 6-84 BUF_VCM_CURR Register Field Descriptions
BitFieldTypeResetDescription
5:4BUF_CURR_CHB__1:0R/W0h ADC channel B input buffer PTAT current source mask LSB's used for gain tracking across temperature for stability.
00b = 19.9uA (default)
01b = 26.5uA
10b = 13.3uA
11b = 19.9uA
100b = 29.9uA
101b = 36.5uA
110b = 23.3uA
111b = 29.9uA
1000b = 6.6uA
1001b = 13.2uA
1010b = 0uA
1011b = 6.6uA
1100b = 16.6uA
1101b = 23.2uA
1110b = 10uA
1111b = 16.6uA
3:0VCM_CURRR/W0h VCM buffer PTAT current source mask used for gain tracking across temperature for stability.
0000b = 19.9uA (default)
0001b = 26.5uA
0010b = 13.3uA
0011b = 19.9uA
0100b = 29.9uA
0101b = 36.5uA
0110b = 23.3uA
0111b = 29.9uA
1000b = 6.6uA
1001b = 13.2uA
1010b = 0uA
1011b = 6.6uA
1100b = 16.6uA
1101b = 23.2uA
1110b = 10uA
1111b = 16.6uA

6.6.1.79 BUF_CURR Register (Address = 30Ah) [Reset = 00h]

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Table 6-85 BUF_CURR Register Field Descriptions
BitFieldTypeResetDescription
6FORMAT_DIGR/W0h Output Data Format when digital features are used.
0b = Two's Complement
1b = Offset binary
5:2BUF_CURR_CHAR/W0h ADC channel A input buffer PTAT current source mask used for gain tracking across temperature for stability.
0000b = 19.9uA (default)
0001b = 26.5uA
0010b = 13.3uA
0011b = 19.9uA
0100b = 29.9uA
0101b = 36.5uA
0110b = 23.3uA
0111b = 29.9uA
1000b = 6.6uA
1001b = 13.2uA
1010b = 0uA
1011b = 6.6uA
1100b = 16.6uA
1101b = 23.2uA
1110b = 10uA
1111b = 16.6uA
1:0BUF_CURR_CHB__3:2R/W0h ADC channel B input buffer PTAT current source mask LSB's used for gain tracking across temperature for stability.
00b = 19.9uA (default)
01b = 26.5uA
10b = 13.3uA
11b = 19.9uA
100b = 29.9uA
101b = 36.5uA
110b = 23.3uA
111b = 29.9uA
1000b = 6.6uA
1001b = 13.2uA
1010b = 0uA
1011b = 6.6uA
1100b = 16.6uA
1101b = 23.2uA
1110b = 10uA
1111b = 16.6uA

6.6.1.80 DEV_CFG_4 Register (Address = 30Bh) [Reset = 00h]

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Table 6-86 DEV_CFG_4 Register Field Descriptions
BitFieldTypeResetDescription
6EXT_REFR/W0h Selects the voltage reference option
0b = Internal reference
1b = External reference
5SE_ENR/W0h Single ended analog input for ADC channels A and B. In this mode the SNR reduces by 3-dB.
0b = Differential input
1b = Single ended input
4SINGLE_CHR/W0h Disables ADC channel B
0b = ADC channel B enabled
1b = ADC channel B disabled (enforced on single channel devices)
3RESERVEDR0h
2HALF_SPEEDR/W0h Half speed mode (HFSB). Enable when sample clock is less than 65 MSPS.
0b = Half speed mode disabled
1b = Half speed mode enabled (enforced on 25MSPS and 65MSPS devices)
1RESERVEDR0h
08BIT_ENR/W0h ADC resolution
0b = 10-bit resolution
1b = 8-bit resolution

6.6.1.81 GBL_CLK_CFG_1 Register (Address = 484h) [Reset = 0h]

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Table 6-87 GBL_CLK_CFG_1 Register Field Descriptions
BitFieldTypeResetDescription
1CLK_GBLR/W0h Global clock enable. Controls clock for digital block
0b = Gates clock to digital
1b = Ungates clock to digital
0RESERVEDR0h

6.6.1.82 GBL_CLK_CFG_2 Register (Address = 4BEh) [Reset = 00h]

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Table 6-88 GBL_CLK_CFG_2 Register Field Descriptions
BitFieldTypeResetDescription
7:6CLK_STATSR/W0h Controls clock to statistics engine
00b = Disables clock to statistics engine
11b = Enables clock to statistics engine
5:4CLK_COMPR/W0h Controls clock to comparator
00b = Disables clock to comparator
11b = Enables clock to comparator
3:2CLK_DECR/W0h Controls clock to decimation
00b = Disables clock to decimation
11b = Enables clock to decimation
1:0CLK_CCR/W0h Controls clock to channel corrections
00b = Disables clock to channel corrections
11b = Enables clock to channel corrections

6.6.1.83 GBL_CLK_CFG_3 Register (Address = 4BFh) [Reset = 0h]

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Table 6-89 GBL_CLK_CFG_3 Register Field Descriptions
BitFieldTypeResetDescription
1:0CLK_OUTR/W0h Controls clock to digital output block
00b = Disables clock to digital output
11b = Enables clock to digital output