JAJSM24 December 2023 ADC3910D125
PRODMIX
PARAMETER | TEST CONDITIONS | MIN | NOM | MAX | UNIT | |
---|---|---|---|---|---|---|
ADC TIMING SPECIFICATIONS | ||||||
tAD | Aperture Delay | 0.5 | ns | |||
tA | Aperture Jitter | square wave clock with fast edges | 500 | fs | ||
tACQ | Signal acquisition period, referenced to sampling clock falling edge | -TS/5 | Sampling Clock Period | |||
tCONV | Signal conversion period, referenced to sampling clock falling edge | Fs = 25 MSPS | 5.5 | ns | ||
Fs = 65 MSPS | 5.5 | ns | ||||
Fs = 125 MSPS | 5.5 | ns | ||||
Wake up time | Time to valid data after coming out of power down. Internal reference. | 30 | us | |||
Time to valid data after coming out of power down. External 1.2V reference. | 19 | us | ||||
ADC Latency | Signal input to data output | Low Latency Mode (DDR) | 1 | ADC clock cycles | ||
Digital features enabled (SDR, Serial CMOS) | 5 | |||||
Add. Latency | Real Decimation | 2 | 25 | |||
4 | 60 | |||||
8 | 130 | |||||
16 | 270 | |||||
INTERFACE TIMING - DDR CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | TS/4 + 3ns | ns | |||
tCD | DCLK rising edge to output data delay | Fs = 25 MSPS | -11 | -10 | -9 | |
Fs = 65 MSPS | -4.8 | -3.8 | -2.8 | |||
Fs = 125 MSPS | -3 | -2 | -1 | |||
tDV | Data valid | Fs = 25 MSPS | 18 | 20 | 22 | |
Fs = 65 MSPS | 5.7 | 7.7 | 9.7 | |||
Fs = 125 MSPS | 2 | 4 | 6 | |||
INTERFACE TIMING - SDR CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to DCLK rising edge | TS/4 + 3ns | ns | |||
tCD | DCLK rising edge to output data delay | Fs = 25 MSPS | -19 | -20 | -21 | |
Fs = 65 MSPS | -8.6 | -7.6 | -6.6 | |||
Fs = 125 MSPS | -5 | -4 | -3 | |||
tDV | Data valid | Fs = 25 MSPS | 38 | 40 | 42 | |
Fs = 65 MSPS | 13.4 | 15.4 | 17.4 | |||
Fs = 125 MSPS | 6 | 8 | 10 | |||
INTERFACE TIMING - SERIAL CMOS | ||||||
tPD | Propagation delay: sampling clock falling edge to output data delay | Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge |
TS/4 + 3ns | ns | ||
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge |
TS/4 + 3ns | |||||
tCD | DCLK rising edge to output data delay 4 Lane serial CMOS |
Fout = 10 MSPS | -7.25 | -6.25 | -5.25 | ns |
Fout = 20 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 30 MSPS | -3.08 | -2.08 | -1.08 | |||
DCLK rising edge to output data delay 2 Lane serial CMOS |
Fout = 5 MSPS | -7.25 | -6.25 | -5.25 | ||
Fout = 10 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 15 MSPS | -3.08 | -2.08 | -1.08 | |||
tDV | Data valid, 4 Lane serial CMOS | Fout = 10 MSPS | -7.25 | -6.25 | -5.25 | ns |
Fout = 20 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 30 MSPS | -3.08 | -2.08 | -1.08 | |||
Data valid, 2 Lane serial CMOS | Fout = 5 MSPS | -7.25 | -6.25 | -5.25 | ||
Fout = 10 MSPS | -4.125 | -3.125 | -2.125 | |||
Fout = 15 MSPS | -3.08 | -2.08 | -1.08 | |||
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input | ||||||
fCLK,SCLK | Serial clock frequency | 20 | MHz | |||
tS,SEN | SEN falling edge to SCLK rising edge | 10 | ns | |||
tH,SEN | SCLK rising edge to SEN rising edge | 10 | ||||
tS,SDIO | SDIO setup time from rising edge of SCLK | 17 | ||||
tH,SDIO | SDIO hold time from rising edge of SCLK | 9 | ||||
SERIAL PROGRAMMING INTERFACE (SDIO) - Output | ||||||
tOZD | Delay from falling edge of 8th SCLK cycle during read operation for SDIO transition from tri-state to valid data | 3.9 | 10.8 | ns | ||
tODZ | Delay from SEN rising edge for SDIO transition from valid data to tri-state | 3.4 | 14 | |||
tOD | Delay from falling edge of 8th SCLK cycle during read operation to SDIO valid | 3.9 | 10.8 |