JAJSM24A December   2023  – May 2024 ADC3910D025 , ADC3910D065 , ADC3910D125 , ADC3910S025 , ADC3910S065 , ADC3910S125

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics - Power Consumption
    6. 5.6  Electrical Characteristics - DC Specifications
    7. 5.7  Electrical Characteristics - AC Specifications (25 MSPS)
    8. 5.8  Electrical Characteristics - AC Specifications (65 MSPS)
    9. 5.9  Electrical Characteristics - AC Specifications (125 MSPS)
    10. 5.10 Timing Requirements
    11. 5.11 Output Interface Timing Diagram
    12. 5.12 Typical Characteristics - 25MSPS
    13. 5.13 Typical Characteristics - 65MSPS
    14. 5.14 Typical Characteristics - 125MSPS
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 ADC Features
        1. 6.3.1.1 Low Latency Mode
        2. 6.3.1.2 Full Digital Feature Mode
        3. 6.3.1.3 Interleaving Mode
      2. 6.3.2 Analog Input
        1. 6.3.2.1 Single Ended Input
        2. 6.3.2.2 Differential Input
        3. 6.3.2.3 Analog Input Bandwidth
      3. 6.3.3 Sampling Clock Input
      4. 6.3.4 Voltage Reference
      5. 6.3.5 Over-range (OVR)
      6. 6.3.6 Digital Features
        1. 6.3.6.1 Digital Down Converter
          1. 6.3.6.1.1 Digital Down Converter Data Select
          2. 6.3.6.1.2 Decimation Filter
          3. 6.3.6.1.3 DDC Over-range
          4. 6.3.6.1.4 Output Formatting with Decimation
        2. 6.3.6.2 Digital Comparator
          1. 6.3.6.2.1 Comparator Data Select
          2. 6.3.6.2.2 Comparator High and Low Threshold
          3. 6.3.6.2.3 Comparator Configuration Compare Mode
          4. 6.3.6.2.4 Comparator Event Configuration
        3. 6.3.6.3 Statistics Engine
          1. 6.3.6.3.1 Statistics Engine Data Select
          2. 6.3.6.3.2 Window Configuration
        4. 6.3.6.4 Digital Alerts
      7. 6.3.7 Digital Interface
        1. 6.3.7.1 Parallel CMOS Output
        2. 6.3.7.2 Serialized CMOS Output
      8. 6.3.8 Test Patterns
        1. 6.3.8.1 Bypass Test Pattern
        2. 6.3.8.2 Digital Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Power Down Options
    5. 6.5 Programming
      1. 6.5.1 Configuration using the SPI interface
        1. 6.5.1.1 Register Write
        2. 6.5.1.2 Register Read
    6. 6.6 Register Maps
      1. 6.6.1 Register Descriptions
      2. 6.6.2 Statistics Engine Register Map
      3. 6.6.3 Alerts Register Map
  8. 7 Application Information Disclaimer
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Signal Path
        2. 7.2.2.2 Sampling Clock
        3. 7.2.2.3 Voltage Reference
      3. 7.2.3 Application Curves
    3. 7.3 Initialization Set Up
      1. 7.3.1 Register Initialization During Operation
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 ドキュメントの更新通知を受け取る方法
    2. 8.2 サポート・リソース
    3. 8.3 Trademarks
    4. 8.4 静電気放電に関する注意事項
    5. 8.5 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.9 Electrical Characteristics - AC Specifications (125 MSPS)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C,  AVDD = IOVDD = 1.8 V,  FS = 125 MSPS, FIN = 5 MHz, AIN = -1dBFS differential input, Internal 1.2 V reference , and 50% clock duty cycle, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
NSD Noise Spectral Density fIN = 10 MHz, AIN = -20 dBFS -138.8 dBFS/Hz
SNR Signal to noise ratio, excluding DC, HD2 to HD5 fIN = 1.1 MHz 60.8 dBFS
fIN = 5 MHz 57 60.6
fIN = 10 MHz 60.6
fIN = 20 MHz 60.6
fIN = 40 MHz 60.6
fIN = 70 MHz 60.4
SINAD Signal to noise and distortion ratio, excluding DC offset fIN = 1.1 MHz 58.5 dBFS
fIN = 5 MHz 58.9
fIN = 10 MHz 59.1
fIN = 20 MHz 59.1
fIN = 40 MHz 59.6
fIN = 70 MHz 57.7
ENOB Effective number of bits, excluding DC offset fIN = 1.1 MHz 9.8 Bit
fIN = 5 MHz 9.8
fIN = 10 MHz 9.8
fIN = 20 MHz 9.8
fIN = 40 MHz 9.8
fIN = 70 MHz 9.7
THD Total Harmonic Distortion (First five harmonics) fIN = 1.1 MHz -61 dBc
fIN = 5 MHz -63
fIN = 10 MHz -63
fIN = 20 MHz -64
fIN = 40 MHz -65
fIN = 70 MHz -60
SFDR Spur free dynamic range including second and third harmonic fIN = 1.1 MHz 62 dBFS
fIN = 5 MHz 57 64
fIN = 10 MHz 64
fIN = 20 MHz 65
fIN = 40 MHz 67
fIN = 70 MHz 61
SPUR Spur free dynamic range (excluding DC, HD2, HD3) fIN = 1.1 MHz 84 dBFS
fIN = 5 MHz 58 82
fIN = 10 MHz 84
fIN = 20 MHz 82
fIN = 40 MHz 78
fIN = 70 MHz 75
IMD3 Two tone inter-modulation distortion fIN = 10/12 MHz, AIN = -7 dBFS/tone -84 dBc
fIN = 90/92 MHz, AIN = -7 dBFS/tone -97
XTALK Channel-to-channel crosstalk Aggressor = 1.1 MHz 102 dBFS
Aggressor = 10 MHz 90
Aggressor = 20 MHz 98