JAJSM24
December 2023
ADC3910D125
PRODMIX
1
1
特長
2
アプリケーション
3
概要
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics - Power Consumption
5.6
Electrical Characteristics - DC Specifications
5.7
Electrical Characteristics - AC Specifications (25 MSPS)
5.8
Electrical Characteristics - AC Specifications (65 MSPS)
5.9
Electrical Characteristics - AC Specifications (125 MSPS)
5.10
Timing Requirements
5.11
Output Interface Timing Diagram
5.12
Typical Characteristics - 25MSPS
5.13
Typical Characteristics - 65MSPS
5.14
Typical Characteristics - 125MSPS
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
ADC Features
6.3.1.1
Low Latency Mode
6.3.1.2
Full Digital Feature Mode
6.3.1.3
Interleaving Mode
6.3.2
Analog Input
6.3.2.1
Single Ended Input
6.3.2.2
Differential Input
6.3.2.3
Analog Input Bandwidth
6.3.3
Sampling Clock Input
6.3.4
Voltage Reference
6.3.5
Over-range (OVR)
6.3.6
Digital Features
6.3.6.1
Digital Down Converter
6.3.6.1.1
Digital Down Converter Data Select
6.3.6.1.2
Decimation Filter
6.3.6.1.3
DDC Over-range
6.3.6.1.4
Output Formatting with Decimation
6.3.6.2
Digital Comparator
6.3.6.2.1
Comparator Data Select
6.3.6.2.2
Comparator High and Low Threshold
6.3.6.2.3
Comparator Configuration Compare Mode
6.3.6.2.4
Comparator Event Configuration
6.3.6.3
Statistics Engine
6.3.6.3.1
Statistics Engine Data Select
6.3.6.3.2
Window Configuration
6.3.6.4
Digital Alerts
6.3.7
Digital Interface
6.3.7.1
Parallel CMOS Output
6.3.7.2
Serialized CMOS Output
6.3.8
Test Patterns
6.3.8.1
Bypass Test Pattern
6.3.8.2
Digital Test Pattern
6.4
Device Functional Modes
6.4.1
Normal Operation
6.4.2
Power Down Options
6.5
Programming
6.5.1
Configuration using the SPI interface
6.5.1.1
Register Write
6.5.1.2
Register Read
6.6
Register Maps
6.6.1
Register Descriptions
6.6.2
Statistics Engine Register Map
6.6.3
Alerts Register Map
7
Application Information Disclaimer
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.2.1
Input Signal Path
7.2.2.2
Sampling Clock
7.2.2.3
Voltage Reference
7.2.3
Application Curves
7.3
Initialization Set Up
7.3.1
Register Initialization During Operation
7.4
Power Supply Recommendations
7.5
Layout
7.5.1
Layout Guidelines
7.5.2
Layout Example
8
Device and Documentation Support
8.1
ドキュメントの更新通知を受け取る方法
8.2
サポート・リソース
8.3
Trademarks
8.4
静電気放電に関する注意事項
8.5
用語集
9
Revision History
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RSM|32
MPQF195B
サーマルパッド・メカニカル・データ
RSM|32
QFND112H
発注情報
jajsm24_oa
5.11
Output Interface Timing Diagram
Figure 5-1
Timing Diagram: 10-Bit DDR (Default: 10 Lanes)
Figure 5-2
Timing Diagram: 10-Bit SDR (Default: 10 Lanes)
Figure 5-3
Timing Diagram: 12-Bit DDR (Default: 10 Lanes)
Figure 5-4
Timing Diagram: 12-Bit SDR (Default: 10 Lanes)