DLPU040B October 2016 – March 2023 DLP650LNIR , DLPC410
These switches provide controls within the Applications FPGA which impact the DLPC410/DMD modes of operation. For a list of the functions for each switch, see #GUID-DB7C83C1-5F3F-48E8-B123-9B1FBE53849F/T4709747-126.
Switch Number | Effect |
---|---|
1 | ON = Float (Park) all mirrors to the "flat" or "unbiased" state |
2 | ON = counter halt – this freezes the current test pattern on the DMD |
3 | ON = complement data – causes DLPC410 to complement all data received prior to sending to DMD |
4 | ON = north/south flip – causes the DLPC410 to reverse order of row loading, effectively flipping the image |
6 and 5 | Dictates the type of reset being used (where switch 6 is the MSB and ON = 1):
|
7 | ON = Row Address Mode |
8 | ON = Watchdog Timer Enable, disables other resets |