SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

7.4 FLASH Registers

Table 7-19 lists the memory-mapped registers for the FLASH registers. All register offset addresses not listed in Table 7-19 should be considered as reserved locations and the register contents should not be modified.

Table 7-19 FLASH Registers
OffsetAcronymRegister NameSection
28hIMASKInterrupt Mask RegisterGo
30hRISRaw Interrupt Status RegisterGo
38hMISMasked Interrupt Status RegisterGo
40hISETInterrupt Set RegisterGo
48hICLRInterrupt Clear RegisterGo
FChDESCHardware Version Description RegisterGo
100hCMDEXECCommand Execute RegisterGo
104hCMDTYPECommand Type RegisterGo
108hCMDCTLCommand Control RegisterGo
120hCMDADDRCommand Address RegisterGo
124hCMDBYTENCommand Program Byte Enable RegisterGo
130hCMDDATA0Command Data Register 0Go
134hCMDDATA1Command Data Register 1Go
138hCMDDATA2Command Data Register 2Go
13ChCMDDATA3Command Data Register Bits 127:96Go
1D0hCMDWEPROTACommand Write Erase Protect A RegisterGo
1D4hCMDWEPROTBCommand Write Erase Protect B RegisterGo
210hCMDWEPROTNMCommand Write Erase Protect Non-Main RegisterGo
214hCMDWEPROTTRCommand Write Erase Protect Trim RegisterGo
218hCMDWEPROTENCommand Write Erase Protect Engr RegisterGo
3B0hCFGCMDCommand Configuration RegisterGo
3B4hCFGPCNTPulse Counter Configuration RegisterGo
3D0hSTATCMDCommand Status RegisterGo
3D4hSTATADDRAddress Status RegisterGo
3D8hSTATPCNTPulse Count Status RegisterGo
3DChSTATMODEMode Status RegisterGo
3F0hGBLINFO0Global Information Register 0Go
3F4hGBLINFO1Global Information Register 1Go
3F8hGBLINFO2Global Information Register 2Go
400hBANK0INFO0Bank Information Register 0 for Bank 0Go
404hBANK0INFO1Bank Information Register 1 for Bank 0Go

Complex bit access types are encoded to fit into small table cells. Table 7-20 shows the codes that are used for access types in this section.

Table 7-20 FLASH Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

7.4.1 IMASK Register (Offset = 28h) [Reset = 00000000h]

IMASK is shown in Table 7-21.

Return to the Summary Table.

Interrupt Mask Register:
The IMASK register holds the current interrupt mask settings. Masked interrupts
are read in the MIS register. PSD compliant register.

Table 7-21 IMASK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0hReserved
0DONER/W0hInterrupt mask for DONE:
0: Interrupt is disabled in MIS register
1: Interrupt is enabled in MIS register
0h = Interrupt is masked out
1h = Interrupt will request an interrupt service routine and corresponding bit in IPSTANDARD.MIS will be set

7.4.2 RIS Register (Offset = 30h) [Reset = 00000000h]

RIS is shown in Table 7-22.

Return to the Summary Table.

Raw Interrupt Status Register:
The RIS register reflects all pending interrupts, regardless of masking.
The RIS register allows the user to implement a poll scheme. A flag set in this
register can be cleared by writing a 1 to the ICLR register bit even if the
corresponding IMASK bit is not enabled. A flag can be set by software by writing
a 1 to the ISET register. Reading the IIDX register will also clear the
corresponding bit in RIS. PSD compliant register.

Table 7-22 RIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hFlash wrapper operation completed.
This interrupt bit is set by firmware or the corresponding bit in the ISET register.
It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
0h = Interrupt did not occur
1h = Interrupt occurred

7.4.3 MIS Register (Offset = 38h) [Reset = 00000000h]

MIS is shown in Table 7-23.

Return to the Summary Table.

Masked Interrupt Status Register:
The MIS register is a bit-wise AND of the contents of the IMASK and RIS
registers. This is kept mainly for ARM compatibility, and has limited use since
the highest priority interrupt index is returned through the IIDX register.
PSD
compliant register.

Table 7-23 MIS Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hFlash wrapper operation completed.
This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
0h = Masked interrupt did not occur
1h = Masked interrupt occurred

7.4.4 ISET Register (Offset = 40h) [Reset = 00000000h]

ISET is shown in Table 7-24.

Return to the Summary Table.

Interrupt Set Register:
The ISET register allows software to write a 1 to set corresponding interrupt.
Safety:
This meets a safety requirement to allow software diagnostics to trigger
interrupts.
PSD compliant register.

Table 7-24 ISET Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0hReserved
0DONEW0h0: No effect
1: Set the DONE interrupt in the RIS register
0h = Writing a 0 has no effect
1h = Set IPSTANDARD.RIS bit

7.4.5 ICLR Register (Offset = 48h) [Reset = 00000000h]

ICLR is shown in Table 7-25.

Return to the Summary Table.

Interrupt Clear Register.
The ICLR register allows allows software to write a 1 to clear corresponding
interrupt.
PSD compliant register.

Table 7-25 ICLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDW0hReserved
0DONEW0h0: No effect
1: Clear the DONE interrupt in the RIS register
0h = Writing a 0 has no effect
1h = Clear IPSTANDARD.RIS bit

7.4.6 DESC Register (Offset = FCh) [Reset = 0B401010h]

DESC is shown in Table 7-26.

Return to the Summary Table.

Hardware Version Description Register:
This register identifies the flash wrapper hardware version and feature set used.

Table 7-26 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDRB40hModule ID
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR1hFeature set
0h = Minimum Value
Fh = Maximum Value
11-8INSTNUMR0hInstance number
0h = Smallest value
Fh = Highest possible value
7-4MAJREVR1hMajor Revision
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0hMinor Revision
0h = Smallest value
Fh = Highest possible value

7.4.7 CMDEXEC Register (Offset = 100h) [Reset = 00000000h]

CMDEXEC is shown in Table 7-27.

Return to the Summary Table.

Command Execute Register:
Initiates execution of the command specified in the CMDTYPE register.
This register is blocked for writes after being written to 1 and prior to
STATCMD.DONE being set by the flash wrapper hardware.
flash wrapper hardware clears this register after the processing of the command
has completed.

Table 7-27 CMDEXEC Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0hReserved
0VALR/W0hCommand Execute value
Initiates execution of the command specified in the CMDTYPE register.
0h = Command will not execute or is not executing in flash wrapper
1h = Command will execute or is executing in flash wrapper

7.4.8 CMDTYPE Register (Offset = 104h) [Reset = 00000000h]

CMDTYPE is shown in Table 7-28.

Return to the Summary Table.

Command Type Register
This register specifies the type of command to be executed by the flash wrapper
hardware.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Table 7-28 CMDTYPE Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0hReserved
6-4SIZER/W0hCommand size
0h = Operate on 1 flash word
1h = Operate on 2 flash words
2h = Operate on 4 flash words
3h = Operate on 8 flash words
4h = Operate on a flash sector
5h = Operate on an entire flash bank
3RESERVEDR/W0hReserved
2-0COMMANDR/W0hCommand type
0h = No Operation
1h = Program
2h = Erase
4h = Mode Change - Perform a mode change only, no other operation.
5h = Clear Status - Clear status bits in FW_SMSTAT only.
6h = Blank Verify - Check whether a flash word is in the erased state.
This command may only be used with CMDTYPE.SIZE = ONEWORD

7.4.9 CMDCTL Register (Offset = 108h) [Reset = 00000000h]

CMDCTL is shown in Table 7-29.

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Command Control Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Table 7-29 CMDCTL Register Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR/W0hReserved
21DATAVERENR/W0hEnable invalid data verify.
This checks for 0->1 transitions in the memory when
a program operation is initiated. If such a transition is found, the program will
fail with an error without executing the program.
0h = Disable
1h = Enable
20SSERASEDISR/W0hDisable Stair-Step Erase. If set, the default VHV trim voltage setting will be used
for all erase pulses.
By default, this bit is reset, meaning that the VHV voltage will be stepped during
successive erase pulses. The step count, step voltage, begin and end voltages
are all hard-wired.
0h = Enable
1h = Disable
19-17RESERVEDR0hReserved
16ADDRXLATEOVRR/W0hOverride hardware address translation of address in CMDADDR from a
system address to a bank address and bank ID. Use data written to
CMDADDR directly as the bank address. Use the value written to
CMDCTL.BANKSEL directly as the bank ID. Use the value written to
CMDCTL.REGIONSEL directly as the region ID.
0h = Do not override
1h = Override
15-14RESERVEDR0hReserved
13RESERVEDR/W0hReserved
12-9REGIONSELR/W0hBank Region
A specific region ID can be written to this field to indicate to which region an
operation is to be applied if CMDCTL.ADDRXLATEOVR is set.
1h = Main Region
2h = Non-Main Region
4h = Trim Region
8h = Engr Region
8-4RESERVEDR0hReserved
3-0MODESELR/W0hMode
This field is only used for the Mode Change command type. Otherwise, bank
and pump modes are set automaticlly through the NW hardware.
0h = Read Mode
2h = Read Margin 0 Mode
4h = Read Margin 1 Mode
6h = Read Margin 0B Mode
7h = Read Margin 1B Mode
9h = Program Verify Mode
Ah = Program Single Word
Bh = Erase Verify Mode
Ch = Erase Sector
Eh = Program Multiple Word
Fh = Erase Bank

7.4.10 CMDADDR Register (Offset = 120h) [Reset = 00000000h]

CMDADDR is shown in Table 7-30.

Return to the Summary Table.

Command Address Register:
This register forms the target address of a command. The use cases are as
follows:
1) For single-word program, this address indicates the flash bank word to be
programmed.
2) For multi-word program, this address indicates the first flash bank address
for the program. The address will be incremented for further words.
3) For sector erase, this address indicates the sector to be erased.
4) For bank erase, the address indicates the bank to be erased.
Note the address written to this register will be submitted for translation to the
flash wrapper address translation interface, and the translated address
will be used to access the bank. However, if the
CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will
be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Table 7-30 CMDADDR Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hAddress value
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.11 CMDBYTEN Register (Offset = 124h) [Reset = 00000000h]

CMDBYTEN is shown in Table 7-31.

Return to the Summary Table.

Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to
be programmed, a 1 must be written to the corresponding bit in this register.
Normally, all bits are written to 1, allowing program of full flash words.
However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit
or 64-bit portions of a flash word.
During verify, data bytes read from the flash will not be checked if the
corresponding CMDBYTEN bit is 0.
ECC data bytes are protected by the 1-2 MSB bits in this register, depending on
the presence of ECC and the flash word data width.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is written to all 0 after the completion of all flash wrapper commands.

Table 7-31 CMDBYTEN Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0hReserved
17-16RESERVEDR0hReserved
15-0VALR/W0hCommand Byte Enable value.
A 1-bit per flash word byte value is placed in this register.
0h = Minimum value of VAL
0003FFFFh = Maximum value of VAL

7.4.12 CMDDATA0 Register (Offset = 130h) [Reset = FFFFFFFFh]

CMDDATA0 is shown in Table 7-32.

Return to the Summary Table.

Command Data Register 0
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-32 CMDDATA0 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.13 CMDDATA1 Register (Offset = 134h) [Reset = FFFFFFFFh]

CMDDATA1 is shown in Table 7-33.

Return to the Summary Table.

Command Data Register 1
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to CMDSTAT.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-33 CMDDATA1 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.14 CMDDATA2 Register (Offset = 138h) [Reset = FFFFFFFFh]

CMDDATA2 is shown in Table 7-34.

Return to the Summary Table.

Command Data Register 2
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-34 CMDDATA2 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.15 CMDDATA3 Register (Offset = 13Ch) [Reset = FFFFFFFFh]

CMDDATA3 is shown in Table 7-35.

Return to the Summary Table.

Command Data Register 3
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.

Table 7-35 CMDDATA3 Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.16 CMDWEPROTA Register (Offset = 1D0h) [Reset = FFFFFFFFh]

CMDWEPROTA is shown in Table 7-36.

Return to the Summary Table.

Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from
program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32
sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-36 CMDWEPROTA Register Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the flash memory will be protected from program
and erase.
bit [1]: When 1, sector 1 of the flash memory will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the flash memory will be protected from program
and erase.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.17 CMDWEPROTB Register (Offset = 1D4h) [Reset = 0FFFFFFFh]

CMDWEPROTB is shown in Table 7-37.

Return to the Summary Table.

Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and
erase. Each bit corresponds to a group of 8 sectors.
There are 3 cases for how these protect bits are applied:
1. Single-bank system:
In the case where only a single flash bank is present,
the first 32 sectors are protected via the CMDWEPROTA register. Thus, the
protection give by the bits in CMDWEPROTB begin with sector 32.
2. Multi-bank system, Bank 0:
When multiple flash banks are present, the first
32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only
bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of
bit 4 and above would begin at sector 32. Bits 3:0
of WEPROTB are ignored for bank 0.
3. Multi-bank system, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has
no effect, so the bits in CMDWEPROTB will protect these banks starting
from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-37 CMDWEPROTB Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-0VALR/W0FFFFFFFhEach bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors
in the flash will be protected from program and erase. A maximum of 256
sectors can be protected with this register.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.18 CMDWEPROTNM Register (Offset = 210h) [Reset = 00000001h]

CMDWEPROTNM is shown in Table 7-38.

Return to the Summary Table.

Command WriteErase Protect Non-Main
Register
This register allows non-main region region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-38 CMDWEPROTNM Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1hEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the non-main region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the non-main region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the non-main will be protected from program
and erase.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.19 CMDWEPROTTR Register (Offset = 214h) [Reset = 00000001h]

CMDWEPROTTR is shown in Table 7-39.

Return to the Summary Table.

Command WriteErase Protect Trim
Register
This register allows trim region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-39 CMDWEPROTTR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1hEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the engr region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the engr region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the engr region will be protected from program
and erase.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.20 CMDWEPROTEN Register (Offset = 218h) [Reset = 00000001h]

CMDWEPROTEN is shown in Table 7-40.

Return to the Summary Table.

Command WriteErase Protect Engr
Register
This register allows engr region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Table 7-40 CMDWEPROTEN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1hEach bit protects 1 sector.
bit [0]: When 1, sector 0 of the engr region will be protected from program
and erase.
bit [1]: When 1, sector 1 of the engr region will be protected from program
and erase.
:
:
bit [31]: When 1, sector 31 of the engr region will be protected from program
and erase.
0h = Minimum value of VAL
FFFFFFFFh = Maximum value of VAL

7.4.21 CFGCMD Register (Offset = 3B0h) [Reset = 00000002h]

CFGCMD is shown in Table 7-41.

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Command Configuration Register
This register configures specific capabilities of the state machine for related to
the execution of a command.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Table 7-41 CFGCMD Register Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR/W0hReserved
6-4RESERVEDR0hReserved
3-0WAITSTATER/W2hWait State setting for verify reads
0h = Minimum value
Fh = Maximum value

7.4.22 CFGPCNT Register (Offset = 3B4h) [Reset = 00000000h]

CFGPCNT is shown in Table 7-42.

Return to the Summary Table.

Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for
program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Table 7-42 CFGPCNT Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0hReserved
19-17RESERVEDR/W0hReserved
16RESERVEDR0hReserved
15-12RESERVEDR/W0hReserved
11-4MAXPCNTVALR/W0hOverride maximum pulse counter with this value.
If MAXPCNTOVR = 0, then this field is ignored.
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used
to override the max pulse count for both program and erase. Full max value
will be {4'h0, MAXPCNTVAL} .
If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used
to override the max pulse count for program only. Full max value will be
{4'h0, MAXPCNTVAL}.
0h = Minimum value
FFh = Maximum value
3-1RESERVEDR/W0hReserved
0MAXPCNTOVRR/W0hOverride hard-wired maximum pulse count. If MAXERSPCNTOVR
is not set, then setting this value alone will override the max pulse count for
both program and erase. If MAXERSPCNTOVR is set, then this bit will only
control the max pulse count setting for program.
By default, this bit is 0, and a hard-wired max pulse count is used.
0h = Use hard-wired (default) value for maximum pulse count
1h = Use value from MAXPCNTVAL field as maximum puse count

7.4.23 STATCMD Register (Offset = 3D0h) [Reset = 00000000h]

STATCMD is shown in Table 7-43.

Return to the Summary Table.

Command Status Register
This register contains status regarding completion and errors of command
execution.

Table 7-43 STATCMD Register Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12FAILMISCR0hCommand failed due to error other than write/erase protect violation or verify
error. This is an extra bit in case a new failure mechanism is added which
requires a status bit.
0h = No Fail
1h = Fail
11-9RESERVEDR0hReserved
8FAILINVDATAR0hProgram command failed because an attempt was made to program a stored
0 value to a 1.
0h = No Fail
1h = Fail
7FAILMODER0hCommand failed because a bank has been set to a mode other than READ.
Program and Erase commands cannot be initiated unless all banks are in READ
mode.
0h = No Fail
1h = Fail
6FAILILLADDRR0hCommand failed due to the use of an illegal address
0h = No Fail
1h = Fail
5FAILVERIFYR0hCommand failed due to verify error
0h = No Fail
1h = Fail
4FAILWEPROTR0hCommand failed due to Write/Erase Protect Sector Violation
0h = No Fail
1h = Fail
3RESERVEDR0hReserved
2CMDINPROGRESSR0hCommand In Progress
0h = Complete
1h = In Progress
1CMDPASSR0hCommand Pass - valid when CMD_DONE field is 1
0h = Fail
1h = Pass
0CMDDONER0hCommand Done
0h = Not Done
1h = Done

7.4.24 STATADDR Register (Offset = 3D4h) [Reset = 00210000h]

STATADDR is shown in Table 7-44.

Return to the Summary Table.

Current Address Counter Value
Read only register giving read access to the state machine current address.
A bank id, region id and address are stored in this register and are incremented as
necessary during execution of a command.

Table 7-44 STATADDR Register Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-21BANKIDR1hCurrent Bank ID
A bank indicator is stored in this register which represents the current bank on
which the state machine is operating. There is 1 bit per bank.
1h = Bank 0
2h = Bank 1
4h = Bank 2
8h = Bank 3
10h = Bank 4
20-16REGIONIDR1hCurrent Region ID
A region indicator is stored in this register which represents the current flash
region on which the state machine is operating.
1h = Main Region
2h = Non-Main Region
4h = Trim Region
8h = Engr Region
15-0BANKADDRR0hCurrent Bank Address
A bank offset address is stored in this register.
0h = Minimum value
FFFFh = Maximum value

7.4.25 STATPCNT Register (Offset = 3D8h) [Reset = 00000000h]

STATPCNT is shown in Table 7-45.

Return to the Summary Table.

Current Pulse Count Register:
Read only register giving read access to the state machine current pulse count
value for program/erase operations.

Table 7-45 STATPCNT Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0PULSECNTR0hCurrent Pulse Counter Value
0h = Minimum value
FFFh = Maximum value

7.4.26 STATMODE Register (Offset = 3DCh) [Reset = 00000000h]

STATMODE is shown in Table 7-46.

Return to the Summary Table.

Mode Status Register
Indicates one or more banks which not in READ mode, and it indicates the mode
which the bank(s) are in.

Table 7-46 STATMODE Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17BANK1TRDYR0hBank 1T Ready.
Bank(s) are ready for 1T access. This is accomplished when the bank and pump
have been trimmed.
0h = Not ready
1h = Ready
16BANK2TRDYR0hBank 2T Ready.
Bank(s) are ready for 2T access. This is accomplished when the pump has
fully driven power rails to the bank(s).
0h = Not ready
1h = Ready
15-12RESERVEDR0hReserved
11-8BANKMODER0hIndicates mode of bank(s) that are not in READ mode
0h = Read Mode
2h = Read Margin 0 Mode
4h = Read Margin 1 Mode
6h = Read Margin 0B Mode
7h = Read Margin 1B Mode
9h = Program Verify Mode
Ah = Program Single Word
Bh = Erase Verify Mode
Ch = Erase Sector
Eh = Program Multiple Word
Fh = Erase Bank
7-5RESERVEDR0hReserved
4-1RESERVEDR0hReserved
0BANKNOTINRDR0hBank not in read mode.
Indicates which banks are not in READ mode. There is 1 bit per bank.
1h = Bank 0
2h = Bank 1
4h = Bank 2
8h = Bank 3
10h = Bank 4

7.4.27 GBLINFO0 Register (Offset = 3F0h) [Reset = 00010800h]

GBLINFO0 is shown in Table 7-47.

Return to the Summary Table.

Global Info 0 Register
Read only register detailing information about sector size and number of banks
present.

Table 7-47 GBLINFO0 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16NUMBANKSR1hNumber of banks instantiated
Minimum: 1
Maximum: 5
1h = Minimum value
5h = Maximum value
15-0SECTORSIZER800hSector size in bytes
400h = Sector size is ONEKB
800h = Sector size is TWOKB

7.4.28 GBLINFO1 Register (Offset = 3F4h) [Reset = 00040080h]

GBLINFO1 is shown in Table 7-48.

Return to the Summary Table.

Global Info 1 Register
Read only register detailing information about data, ecc and redundant data
widths in bits.

Table 7-48 GBLINFO1 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16REDWIDTHR4hRedundant data width in bits
0h = Redundant data width is 0. Redundancy/Repair not present.
2h = Redundant data width is 2 bits
4h = Redundant data width is 4 bits
15-13RESERVEDR0hReserved
12-8ECCWIDTHR0hECC data width in bits
0h = ECC data width is 0. ECC not used.
8h = ECC data width is 8 bits
10h = ECC data width is 16 bits
7-0DATAWIDTHR80hData width in bits
40h = Data width is 64 bits
80h = Data width is 128 bits

7.4.29 GBLINFO2 Register (Offset = 3F8h) [Reset = 00000001h]

GBLINFO2 is shown in Table 7-49.

Return to the Summary Table.

Global Info 2 Register
Read only register detailing information about the number of data registers
present.

Table 7-49 GBLINFO2 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0DATAREGISTERSR1hNumber of data registers present.
1h = Minimum value of DATAREGISTERS
8h = Maximum value of DATAREGISTERS

7.4.30 BANK0INFO0 Register (Offset = 400h) [Reset = 00000100h]

BANK0INFO0 is shown in Table 7-50.

Return to the Summary Table.

Bank Info 0 Register for bank 0.
Read only register detailing information about Main region size in the bank.

Table 7-50 BANK0INFO0 Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER100hMain region size in sectors
Minimum: 0x8 (8)
Maximum: 0x200 (512)
8h = Minimum value of MAINSIZE
200h = Maximum value of MAINSIZE

7.4.31 BANK0INFO1 Register (Offset = 404h) [Reset = 00010101h]

BANK0INFO1 is shown in Table 7-51.

Return to the Summary Table.

Bank Info1 Register for bank 0.
Read only register detailing information about Non-Main, Trim, and Engr
region sizes in the bank.

Table 7-51 BANK0INFO1 Register Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER1hEngr region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
0h = Minimum value of ENGRSIZE
20h = Maximum value of ENGRSIZE
15-8TRIMSIZER1hTrim region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
0h = Minimum value of TRIMSIZE
20h = Maximum value of TRIMSIZE
7-0NONMAINSIZER1hNon-main region size in sectors
Minimum: 0x0 (0)
Maximum: 0x10 (16)
0h = Minimum value of NONMAINSIZE
20h = Maximum value of NONMAINSIZE