SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
Figure 20-7 shows the MICROWIRE frame format for a single frame. Figure 20-8 shows the same format when back-to-back frames are transmitted.
MICROWIRE format is similar to SPI format, except that transmission is half-duplex and uses a controller-peripheral message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SPI to the off-chip peripheral device. During this transmission, the SPI does not receive incoming data. After the message is sent, the off-chip peripheral decodes the message and waits one serial clock after the last bit of the 8-bit control message is sent. The off-chip peripheral then responds with the required data. The returned data is 4 to 16 bits long, making the total frame length anywhere from 13 to 25 bits.
In this configuration, the following occurs during idle periods:
Writing a control byte to the TX FIFO triggers a transmission. The falling edge of CS transfers the value of the TX FIFO to the serial shift register of the transmit logic and shifts the MSB of the 8-bit control frame out onto the PICO pin. CS remains low for the duration of the frame transmission. The POCI pin remains in the tri-state condition during this transmission.
The off-chip serial peripheral device latches each control bit into the serial shifter on each rising edge of SCLK. After the last bit is latched by the peripheral device, the control byte is decoded during a one clock wait state and the peripheral responds by transmitting data back to the SPI. Each bit is driven onto the POCI line on the falling edge of SCLK. The SPI latches each bit on the rising edge of SCLK. At the end of the frame for single transfers, the CS signal is pulled high one clock period after the last bit is latched in the receive serial shifter transferring the data to the RX FIFO.
For continuous transfers, data transmission begins and ends like a single transfer, but the CS line is held low and data transmits back-to-back. The control byte of the next frame follows the LSB of the received data from the current frame. After the LSB of the frame is latched into the SPI, each received value is transferred from the receive shifter on the falling edge of SCLK.
In the MICROWIRE mode, the SPI peripheral samples the first bit of receive data on the rising edge of SCLK after CS has gone low. Controllers driving a free-running SCLK must ensure that the CS signal has sufficient setup and hold margins with respect to the rising edge of SCLK.