SWCU193 April   2023 CC2340R2 , CC2340R5 , CC2340R5-Q1

 

  1.   Read This First
    1.     About This Manual
    2.     Devices
    3.     Register, Field, and Bit Calls
    4.     Related Documentation
    5.     Trademarks
  2. 1 Architectural Overview
    1. 1.1  Target Applications
    2. 1.2  Introduction
    3. 1.3  Arm Cortex M0+
      1. 1.3.1 Processor Core
      2. 1.3.2 SysTick Timer
      3. 1.3.3 Nested Vectored Interrupt Controller
      4. 1.3.4 System Control Block (SCB)
    4. 1.4  On-Chip Memory
      1. 1.4.1 SRAM
      2. 1.4.2 FLASH
      3. 1.4.3 ROM
    5. 1.5  Power Supply System
      1. 1.5.1 VDDS
      2. 1.5.2 VDDR
      3. 1.5.3 VDDD Digital Core Supply
      4. 1.5.4 DC/DC Converter
    6. 1.6  Radio
    7. 1.7  AES 128-bit Cryptographic Accelerator
    8. 1.8  System Timer (SYSTIM)
    9. 1.9  General Purpose Timers (LGPT)
    10. 1.10 Always-ON (AON) or Ultra-Low Leakage (ULL) Domain
      1. 1.10.1 Watchdog Timer
      2. 1.10.2 Battery and Temperature Monitor
      3. 1.10.3 Real-time Clock (RTC)
      4. 1.10.4 Low Power Comparator
    11. 1.11 Direct Memory Access
    12. 1.12 System Control and Clock
    13. 1.13 Communication Peripherals
      1. 1.13.1 UART
      2. 1.13.2 I2C
      3. 1.13.3 SPI
    14. 1.14 Programmable I/Os
    15. 1.15 Serial Wire Debug (SWD)
  3. 2  Arm Cortex-M0+ Processor
    1. 2.1 Introduction
    2. 2.2 Block Diagram
    3. 2.3 Overview
      1. 2.3.1 Peripherals
      2. 2.3.2 Programmer's Model
      3. 2.3.3 Instruction Set Summary
      4. 2.3.4 Memory Model
    4. 2.4 Registers
      1. 2.4.1 BPU Registers
      2. 2.4.2 CPU_ROM_TABLE Registers
      3. 2.4.3 DCB Registers
      4. 2.4.4 SCB Registers
      5. 2.4.5 SCSCS Registers
      6. 2.4.6 NVIC Registers
      7. 2.4.7 SYSTICK Registers
  4. 3 Memory Map
    1. 3.1 Memory Map
  5. 4 Interrupts and Events
    1. 4.1 Exception Model
      1. 4.1.1 Exception States
      2. 4.1.2 Exception Types
      3. 4.1.3 Exception Handlers
      4. 4.1.4 Vector Table
      5. 4.1.5 Exception Priorities
      6. 4.1.6 Exception Entry and Return
        1. 4.1.6.1 Exception Entry
        2. 4.1.6.2 Exception Return
    2. 4.2 Fault Handling
      1. 4.2.1 Lockup
    3. 4.3 Event Fabric
      1. 4.3.1 Introduction
      2. 4.3.2 Overview
      3. 4.3.3 Registers
      4. 4.3.4 AON Event Fabric
        1. 4.3.4.1 AON Common Input Events List
        2. 4.3.4.2 AON Event Subscribers
        3. 4.3.4.3 Power Management Controller (PMCTL)
        4. 4.3.4.4 Real Time Clock (RTC)
        5. 4.3.4.5 AON to MCU Event Fabric
      5. 4.3.5 MCU Event Fabric
        1. 4.3.5.1 Common Input Event List
        2. 4.3.5.2 MCU Event Subscribers
          1. 4.3.5.2.1 System CPU
          2. 4.3.5.2.2 Non-Maskable Interrupt (NMI)
    4. 4.4 Digital Test Bus (DTB)
    5. 4.5 EVTULL Registers
    6. 4.6 EVTSVT Registers
  6. 5 Debug Subsystem
    1. 5.1  Introduction
    2. 5.2  Block Diagram
    3. 5.3  Overview
      1. 5.3.1 Physical Interface
      2. 5.3.2 Debug Access Ports
    4. 5.4  Debug Features
      1. 5.4.1 Processor Debug
      2. 5.4.2 Breakpoint Unit (BPU)
      3. 5.4.3 Peripheral Debug
    5. 5.5  Behavior in Low Power Modes
    6. 5.6  Restricting Debug Access
    7. 5.7  Mailbox (DSSM)
    8. 5.8  Mailbox Events
      1. 5.8.1 CPU Interrupt Event (AON_DBG_COMB)
    9. 5.9  Software Considerations
    10. 5.10 DBGSS Registers
  7. 6 Power, Reset, and Clocking
    1. 6.1  Introduction
    2. 6.2  System CPU Modes
    3. 6.3  Supply System
      1. 6.3.1 Internal DC/DC Converter and Global LDO
    4. 6.4  Power States
      1. 6.4.1 RESET
      2. 6.4.2 SHUTDOWN
      3. 6.4.3 ACTIVE
      4. 6.4.4 IDLE
      5. 6.4.5 STANDBY
    5. 6.5  Digital Power Partitioning
    6. 6.6  Clocks
      1. 6.6.1 CLKSVT
      2. 6.6.2 CLKULL
    7. 6.7  Resets
      1. 6.7.1 Watchdog Timer (WDT)
      2. 6.7.2 LF Loss Detection
    8. 6.8  AON (REG3V3) Register Bank
    9. 6.9  CKMD Registers
    10. 6.10 CLKCTL Registers
    11. 6.11 PMCTL Registers
  8. 7 Internal Memory
    1. 7.1 SRAM
    2. 7.2 VIMS
      1. 7.2.1 Introduction
      2. 7.2.2 Block Diagram
      3. 7.2.3 Cache
        1. 7.2.3.1 Basic Cache Mechanism
        2. 7.2.3.2 Cache Prefetch Mechanism
        3. 7.2.3.3 Cache Micro-Prediction Mechanism
      4. 7.2.4 FLASH
        1. 7.2.4.1 FLASH Read-Only Protection
        2. 7.2.4.2 FLASH Memory Programming
      5. 7.2.5 ROM
    3. 7.3 VIMS Registers
    4. 7.4 FLASH Registers
  9. 8 Device Boot and Bootloader
    1. 8.1 Device Boot and Programming
      1. 8.1.1 Boot Flow
      2. 8.1.2 Boot Timing
      3. 8.1.3 Boot Status
      4. 8.1.4 Boot Protection/Locking Mechanisms
      5. 8.1.5 Debug and Active SWD Connections at Boot
      6. 8.1.6 Flashless Test Mode and Tools Client Mode
        1. 8.1.6.1 Flashless Test Mode
        2. 8.1.6.2 Tools Client Mode
      7. 8.1.7 Retest Mode and Return-to-Factory Procedure
      8. 8.1.8 Disabling SWD Debug Port
    2. 8.2 Flash Programming
      1. 8.2.1 CCFG
      2. 8.2.2 CCFG Permissions/Restrictions that Affect Flash Programming
      3. 8.2.3 SACI Flash Programming Commands
      4. 8.2.4 Flash Programming Flows
        1. 8.2.4.1 Initial Programming of a New Device
        2. 8.2.4.2 Reprogramming of Previously Programmed Device
        3. 8.2.4.3 Add User Record on Already Programmed Device as Part of Commissioning Step
        4. 8.2.4.4 Incrementally Program Ancillary Data to MAIN Flash Sectors of a Previously Programmed Device
    3. 8.3 Device Management Command Interface
      1. 8.3.1 SACI Communication Protocol
        1. 8.3.1.1 Host Side Protocol
        2. 8.3.1.2 Command Format
        3. 8.3.1.3 Response Format
        4. 8.3.1.4 Response Result Field
        5. 8.3.1.5 Command Sequence Tag
        6. 8.3.1.6 Host Side Timeout
      2. 8.3.2 SACI Commands
        1. 8.3.2.1 Miscellaneous Commands
          1. 8.3.2.1.1 SACI_CMD_MISC_NO_OPERATION
          2. 8.3.2.1.2 SACI_CMD_MISC_GET_DIE_ID
          3. 8.3.2.1.3 SACI_CMD_MISC_GET_CCFG_USER_REC
        2. 8.3.2.2 Debug Commands
          1. 8.3.2.2.1 SACI_CMD_DEBUG_REQ_PWD_ID
          2. 8.3.2.2.2 SACI_CMD_DEBUG_SUBMIT_AUTH
          3. 8.3.2.2.3 SACI_CMD_DEBUG_EXIT_SACI_HALT
          4. 8.3.2.2.4 SACI_CMD_DEBUG_EXIT_SACI_SHUTDOWN
          5. 8.3.2.2.5 SACI_CMD_BLDR_APP_RESET_DEVICE
          6. 8.3.2.2.6 SACI_CMD_BLDR_APP_EXIT_SACI_RUN
        3. 8.3.2.3 Flash Programming Commands
          1. 8.3.2.3.1 SACI_CMD_FLASH_ERASE_CHIP
          2. 8.3.2.3.2 SACI_CMD_FLASH_PROG_CCFG_SECTOR
          3. 8.3.2.3.3 SACI_CMD_FLASH_PROG_CCFG_USER_REC
          4. 8.3.2.3.4 SACI_CMD_FLASH_PROG_MAIN_SECTOR
          5. 8.3.2.3.5 SACI_CMD_FLASH_PROG_MAIN_PIPELINED
          6. 8.3.2.3.6 SACI_CMD_FLASH_VERIFY_MAIN_SECTORS
          7. 8.3.2.3.7 SACI_CMD_FLASH_VERIFY_CCFG_SECTOR
    4. 8.4 Bootloader Support
      1. 8.4.1 Bootloader Parameters
      2. 8.4.2 Persistent State
      3. 8.4.3 User-Defined Bootloader Guidelines
    5. 8.5 ROM Serial Bootloader
      1. 8.5.1 ROM Serial Bootloader Interfaces
        1. 8.5.1.1 Packet Handling
          1. 8.5.1.1.1 Packet Acknowledge and Not-Acknowledge Bytes
        2. 8.5.1.2 Transport Layer
          1. 8.5.1.2.1 UART Transport
            1. 8.5.1.2.1.1 UART Baud Rate Automatic Detection
          2. 8.5.1.2.2 SPI Transport
      2. 8.5.2 ROM Serial Bootloader Parameters
      3. 8.5.3 ROM Serial Bootloader Commands
        1. 8.5.3.1 BLDR_CMD_PING
        2. 8.5.3.2 BLDR_CMD_GET_STATUS
        3. 8.5.3.3 BLDR_CMD_GET_PART_ID
        4. 8.5.3.4 BLDR_CMD_RESET
        5. 8.5.3.5 BLDR_CMD_CHIP_ERASE
        6. 8.5.3.6 BLDR_CMD_CRC32
        7. 8.5.3.7 BLDR_CMD_DOWNLOAD
        8. 8.5.3.8 BLDR_CMD_DOWNLOAD_CRC
        9. 8.5.3.9 BLDR_CMD_SEND_DATA
      4. 8.5.4 Bootloader Firmware Update Example
  10. 9 Device Configuration
    1. 9.1 Factory Configuration (FCFG)
    2. 9.2 Customer Configuration (CCFG)
  11. 10General Purpose Timers (LGPT)
    1. 10.1 Overview
    2. 10.2 Block Diagram
    3. 10.3 Functional Description
      1. 10.3.1  Prescaler
      2. 10.3.2  Counter
      3. 10.3.3  Target
      4. 10.3.4  Channel Input Logic
      5. 10.3.5  Channel Output Logic
      6. 10.3.6  Channel Actions
        1. 10.3.6.1 Period and Pulse Width Measurement
        2. 10.3.6.2 Clear on Zero, Toggle on Compare Repeatedly
        3. 10.3.6.3 Set on Zero, Toggle on Compare Repeatedly
      7. 10.3.7  Channel Capture Configuration
      8. 10.3.8  Channel Filters
        1. 10.3.8.1 Setting up the Channel Filters
      9. 10.3.9  Synchronize Multiple LGPT Timers
      10. 10.3.10 Interrupts, ADC Trigger, and DMA Request
    4. 10.4 Timer Modes
      1. 10.4.1 Quadrature Decoder
      2. 10.4.2 DMA
      3. 10.4.3 IR Generation
      4. 10.4.4 Fault and Park
      5. 10.4.5 Dead-Band
      6. 10.4.6 Dead-Band, Fault and Park
      7. 10.4.7 Example Application: Brushless DC (BLDC) Motor
    5. 10.5 LGPT0 Registers
    6. 10.6 LGPT1 Registers
    7. 10.7 LGPT2 Registers
    8. 10.8 LGPT3 Registers
  12. 11System Timer (SYSTIM)
    1. 11.1 Overview
    2. 11.2 Block Diagram
    3. 11.3 Functional Description
      1. 11.3.1 Common Channel Features
        1. 11.3.1.1 Compare Mode
        2. 11.3.1.2 Capture Mode
        3. 11.3.1.3 Additional Channel Arming Methods
      2. 11.3.2 Interrupts and Events
    4. 11.4 SYSTIM Registers
  13. 12Real Time Clock (RTC)
    1. 12.1 Introduction
    2. 12.2 Block Diagram
    3. 12.3 Interrupts and Events
      1. 12.3.1 Input Event
      2. 12.3.2 Output Event
      3. 12.3.3 Arming and Disarming Channels
    4. 12.4 Capture and Compare Configuration
      1. 12.4.1 Capture
      2. 12.4.2 Compare
    5. 12.5 RTC Registers
  14. 13Low Power Comparator
    1. 13.1 Introduction
    2. 13.2 Block Diagram
    3. 13.3 Functional Description
      1. 13.3.1 Input Selection
      2. 13.3.2 Voltage Divider
      3. 13.3.3 Hysteresis
      4. 13.3.4 Wake-up
    4. 13.4 SYS0 Registers
  15. 14Battery Monitor, Temperature Sensor, and DCDC Controller (PMUD)
    1. 14.1 Introduction
    2. 14.2 Functional Description
      1. 14.2.1 BATMON
      2. 14.2.2 DCDC
    3. 14.3 PMUD Registers
  16. 15Micro Direct Memory Access (µDMA)
    1. 15.1 Introduction
    2. 15.2 Block Diagram
    3. 15.3 Functional Description
      1. 15.3.1  Channel Assignments
      2. 15.3.2  Priority
      3. 15.3.3  Arbitration Size
      4. 15.3.4  Request Types
        1. 15.3.4.1 Single Request
        2. 15.3.4.2 Burst Request
      5. 15.3.5  Channel Configuration
      6. 15.3.6  Transfer Modes
        1. 15.3.6.1 Stop Mode
        2. 15.3.6.2 Basic Mode
        3. 15.3.6.3 Auto Mode
        4. 15.3.6.4 Ping-Pong Mode
        5. 15.3.6.5 Memory Scatter-Gather Mode
        6. 15.3.6.6 Peripheral Scatter-Gather Mode
      7. 15.3.7  Transfer Size and Increments
      8. 15.3.8  Peripheral Interface
      9. 15.3.9  Software Request
      10. 15.3.10 Interrupts and Errors
      11. 15.3.11 Initialization and Configuration
        1. 15.3.11.1 Module Initialization
        2. 15.3.11.2 Configuring a Memory-to-Memory Transfer
        3. 15.3.11.3 Configure the Channel Attributes
        4. 15.3.11.4 Configure the Channel Control Structure
        5. 15.3.11.5 Start the Transfer
        6. 15.3.11.6 Software Considerations
    4. 15.4 DMA Registers
  17. 16Advanced Encryption Standard (AES)
    1. 16.1 Introduction
      1. 16.1.1 AES Performance
    2. 16.2 Functional Description
      1. 16.2.1 Reset Considerations
      2. 16.2.2 Interrupt and Event Support
        1. 16.2.2.1 Interrupt Events and Requests
        2. 16.2.2.2 Connection to Event Fabric
      3. 16.2.3 µDMA
        1. 16.2.3.1 µDMA Example
    3. 16.3 Encryption and Decryption Configuration
      1. 16.3.1  CBC-MAC (Cipher Block Chaining-Message Authentication Code)
      2. 16.3.2  CBC (Cipher Block Chaining) Encryption
      3. 16.3.3  CBC Decryption
      4. 16.3.4  CTR (Counter) Encryption/Decryption
      5. 16.3.5  ECB (Electronic Code Book) Encryption
      6. 16.3.6  ECB Decryption
      7. 16.3.7  CFB (Cipher Feedback) Encryption
      8. 16.3.8  CFB Decryption
      9. 16.3.9  OFB (Open Feedback) Encryption
      10. 16.3.10 OFB Decryption
      11. 16.3.11 PCBC (Propagating Cipher Block Chaining) Encryption
      12. 16.3.12 PCBC Decryption
      13. 16.3.13 CTR-DRBG (Counter-Deterministic Random Bit Generator)
      14. 16.3.14 CCM
    4. 16.4 AES Registers
  18. 17Analog to Digital Converter (ADC)
    1. 17.1 Overview
    2. 17.2 Block Diagram
    3. 17.3 Functional Description
      1. 17.3.1  ADC Core
      2. 17.3.2  Voltage Reference Options
      3. 17.3.3  Resolution Modes
      4. 17.3.4  ADC Clocking
      5. 17.3.5  Power Down Behavior
      6. 17.3.6  Sampling Trigger Sources and Sampling Modes
        1. 17.3.6.1 AUTO Sampling Mode
        2. 17.3.6.2 MANUAL Sampling Mode
      7. 17.3.7  Sampling Period
      8. 17.3.8  Conversion Modes
      9. 17.3.9  ADC Data Format
      10. 17.3.10 Status Register
      11. 17.3.11 ADC Events
        1. 17.3.11.1 CPU Interrupt Event Publisher (INT_EVENT0)
        2. 17.3.11.2 Generic Event Publisher (INT_EVENT1)
        3. 17.3.11.3 DMA Trigger Event Publisher (INT_EVENT2)
        4. 17.3.11.4 Generic Event Subscriber
    4. 17.4 Advanced Features
      1. 17.4.1 Window Comparator
      2. 17.4.2 DMA & FIFO Operation
        1. 17.4.2.1 DMA/CPU Operation in Non-FIFO Mode (FIFOEN=0)
        2. 17.4.2.2 DMA/CPU Operation in FIFO Mode (FIFOEN=1)
        3. 17.4.2.3 DMA/CPU Operation Summary Matrix
      3. 17.4.3 Ad-hoc Single Conversion
    5. 17.5 ADC Registers
  19. 18I/O Controller (IOC)
    1. 18.1  Introduction
    2. 18.2  Block Diagram
    3. 18.3  I/O Mapping and Configuration
      1. 18.3.1 Basic I/O Mapping
      2. 18.3.2 Radio GPO
      3. 18.3.3 Pin Mapping
      4. 18.3.4 DTB Muxing
    4. 18.4  Edge Detection
    5. 18.5  GPIO
    6. 18.6  I/O Pins
    7. 18.7  Unused Pins
    8. 18.8  Debug Configuration
    9. 18.9  IOC Registers
    10. 18.10 GPIO Registers
  20. 19Universal Asynchronous Receiver/Transmitter (UART)
    1. 19.1 Introduction
    2. 19.2 Block Diagram
    3. 19.3 Functional Description
      1. 19.3.1 Transmit and Receive Logic
      2. 19.3.2 Baud Rate Generation
      3. 19.3.3 FIFO Operation
        1. 19.3.3.1 FIFO Remapping
      4. 19.3.4 Data Transmission
      5. 19.3.5 Flow Control
      6. 19.3.6 IrDA Encoding and Decoding
      7. 19.3.7 Interrupts
      8. 19.3.8 Loopback Operation
    4. 19.4 Interface to µDMA
    5. 19.5 Initialization and Configuration
    6. 19.6 UART Registers
  21. 20Serial Peripheral Interface (SPI)
    1. 20.1 Overview
      1. 20.1.1 Features
      2. 20.1.2 Block Diagram
    2. 20.2 Signal Description
    3. 20.3 Functional Description
      1. 20.3.1  Clock Control
      2. 20.3.2  FIFO Operation
        1. 20.3.2.1 Transmit FIFO
        2. 20.3.2.2 Repeated Transmit Operation
        3. 20.3.2.3 Receive FIFO
        4. 20.3.2.4 FIFO Flush
      3. 20.3.3  Interrupts
      4. 20.3.4  Data Format
      5. 20.3.5  Delayed Data Sampling
      6. 20.3.6  Chip Select Control
      7. 20.3.7  Command Data Control
      8. 20.3.8  Protocol Descriptions
        1. 20.3.8.1 Motorola SPI Frame Format
        2. 20.3.8.2 Texas Instruments Synchronous Serial Frame Format
        3. 20.3.8.3 MICROWIRE Frame Format
      9. 20.3.9  CRC Configuration
      10. 20.3.10 Auto CRC Functionality
      11. 20.3.11 Auto Header Functionality
      12. 20.3.12 SPI Status
      13. 20.3.13 Debug Halt
    4. 20.4 µDMA Operation
    5. 20.5 Initialization and Configuration
    6. 20.6 SPI Registers
  22. 21Inter-Integrated Circuit (I2C)
    1. 21.1 Introduction
    2. 21.2 Block Diagram
    3. 21.3 Functional Description
      1. 21.3.1 Functional Overview
        1. 21.3.1.1 Start and Stop Conditions
        2. 21.3.1.2 Data Format with 7-Bit Address
        3. 21.3.1.3 Data Validity
        4. 21.3.1.4 Acknowledge
        5. 21.3.1.5 Arbitration
      2. 21.3.2 Available Speed Modes
      3. 21.3.3 Interrupts
        1. 21.3.3.1 I2C Controller Interrupts
        2. 21.3.3.2 I2C Target Interrupts
      4. 21.3.4 Loopback Operation
      5. 21.3.5 Command Sequence Flow Charts
        1. 21.3.5.1 I2C Controller Command Sequences
        2. 21.3.5.2 I2C Target Command Sequences
    4. 21.4 Initialization and Configuration
    5. 21.5 I2C Registers
  23. 22Radio
    1. 22.1 Introduction
    2. 22.2 Block Diagram
    3. 22.3 Overview
      1. 22.3.1 Radio Sub-domains
      2. 22.3.2 Radio RAMs
      3. 22.3.3 Doorbell (DBELL)
        1. 22.3.3.1 Interrupts
        2. 22.3.3.2 GPIO Control
        3. 22.3.3.3 SYSTIM Interface
    4. 22.4 Radio Usage Model
      1. 22.4.1 CRC and Whitening
    5. 22.5 LRFDDBELL Registers
    6. 22.6 LRFDRXF Registers
    7. 22.7 LRFDTXF Registers

6.11 PMCTL Registers

Table 6-71 lists the memory-mapped registers for the PMCTL registers. All register offset addresses not listed in Table 6-71 should be considered as reserved locations and the register contents should not be modified.

Table 6-71 PMCTL Registers
OffsetAcronymRegister NameSection
0hDESCDescription Register.Go
4hDESCEXExtended Description Register.Go
8hSHTDWNShutdown Register.Go
ChSLPCTLSleep Control Register.Go
10hWUSTAWakeup Status RegisterGo
14hVDDRCTLVDDR Control Register.Go
20hSYSFSETInternal. Only to be used through TI provided API.Go
24hSYSFCLRInternal. Only to be used through TI provided API.Go
28hSYSFSTAInternal. Only to be used through TI provided API.Go
2ChRSTCTLReset Control Register.Go
30hRSTSTAReset Status.Go
34hBOOTSTAInternal. Only to be used through TI provided API.Go
3ChAONRSTA1AON Register Status 1.Go
40hAONRSET1AON Register Set 1.Go
44hAONRCLR1AON Register Clear 1.Go
64hETPPInternal. Only to be used through TI provided API.Go
7ChRETCFG0Internal. Only to be used through TI provided API.Go
80hRETCFG1Internal. Only to be used through TI provided API.Go
84hRETCFG2Internal. Only to be used through TI provided API.Go
88hRETCFG3Internal. Only to be used through TI provided API.Go
8ChRETCFG4Internal. Only to be used through TI provided API.Go
90hRETCFG5Internal. Only to be used through TI provided API.Go
94hRETCFG6Internal. Only to be used through TI provided API.Go
98hRETCFG7Internal. Only to be used through TI provided API.Go

Complex bit access types are encoded to fit into small table cells. Table 6-72 shows the codes that are used for access types in this section.

Table 6-72 PMCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.11.1 DESC Register (Offset = 0h) [Reset = D7410010h]

DESC is shown in Table 6-73.

Return to the Summary Table.

Description Register.
This register provides IP module ID, revision information, instance index and standard MMR registers offset.

Table 6-73 DESC Register Field Descriptions
BitFieldTypeResetDescription
31-16MODIDRD741hModule identifier used to uniquely identify this IP.
15-12STDIPOFFR0hStandard IP MMR block offset. Standard IP MMRs are the set of from aggregated IRQ registers till DTB.
0: Standard IP MMRs do not exist
0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP address)
11-8INSTIDXR0hIP Instance ID number. If multiple instances of IP exist in the device, this field can identify the instance number (0-15).
7-4MAJREVR1hMajor revision of IP (0-15).
3-0MINREVR0hMinor revision of IP (0-15).

6.11.2 DESCEX Register (Offset = 4h) [Reset = FC000000h]

DESCEX is shown in Table 6-74.

Return to the Summary Table.

Extended Description Register.
This register shows ULL IP availability and memory size configuration.

Table 6-74 DESCEX Register Field Descriptions
BitFieldTypeResetDescription
31-30FLASHSZR3hSystem flash availability
0h = Flash size set to level 0 (Min size)
1h = Flash size set to level 1
2h = Flash size set to level 2
3h = Flash size set to level 3 (Max size)
29-28SRAMSZR3hSystem SRAM availability
0h = SRAM size set to level 0 (Min size)
1h = SRAM size set to level 1
2h = SRAM size set to level 2
3h = SRAM size set to level 3 (Max size)
27TSDR1h TSD (thermal shutdown) IP status on device
0h = IP is unavailable
1h = IP is available
26LPCMPR1hLPCMP (low power comparator) IP status on device
0h = IP is unavailable
1h = IP is available
25-0RESERVEDR0hReserved

6.11.3 SHTDWN Register (Offset = 8h) [Reset = 00000000h]

SHTDWN is shown in Table 6-75.

Return to the Summary Table.

Shutdown Register.
This register controls SHUTDOWN mode entry.

Table 6-75 SHTDWN Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-0KEYW0hSetting a valid key will trigger the device to enter SHUTDOWN mode.
A5A5h = This is the only valid key value that will trigger SHUTDOWN mode.
All other values are invalid and will have no effect.

6.11.4 SLPCTL Register (Offset = Ch) [Reset = 00000000h]

SLPCTL is shown in Table 6-76.

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Sleep Control Register.
This register controls I/O pad sleep mode. When I/O pad sleep mode is enabled all I/O pad outputs and I/O pad configurations are latched. Inputs are transparent if I/O pad is configured as input.

Table 6-76 SLPCTL Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR/W0hReserved
0SLPNR/W0hThe boot code will set this bit field and disable sleep mode, automatically unless waking up from a SHUTDOWN RSTSTA.SDDET is set.
Application software must reconfigure the state for all IO's before setting this bit field upon waking up from a SHUTDOWN to avoid glitches on pins.
0h = I/O pad sleep mode is enabled
1h = I/O pad sleep mode is disabled

6.11.5 WUSTA Register (Offset = 10h) [Reset = 00000001h]

WUSTA is shown in Table 6-77.

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Wakeup Status Register
This register shows the device wakeup source. Used to distinguish between wakeup from STANDBY, SHUTDOWN and reset.

Table 6-77 WUSTA Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0SRCR1hThis field shows the device wakeup source.
1h = Wakeup from system reset / SHUTDOWN mode.
See RSTSTA for more status information.
2h = Wakeup from STANDBY mode.

6.11.6 VDDRCTL Register (Offset = 14h) [Reset = 00000000h]

VDDRCTL is shown in Table 6-78.

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VDDR Control Register.
This register contains VDDR regulator settings for the device.

Table 6-78 VDDRCTL Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1STBYR/W0hSelect between continuous or duty-cycled VDDR regulation in STANDBY mode.
0h = Duty-cycled VDDR regulation in STANDBY mode.
1h = Continuous VDDR regulation in STANDBY mode.
0SELECTR/W0hSelect between GLDO and DCDC as VDDR regulator (in ACTIVE, IDLE and STANDBY mode).
0h = GLDO enabled for regulation of VDDR voltage
1h = DCDC enabled for regulation of VDDR voltage

6.11.7 SYSFSET Register (Offset = 20h) [Reset = 00000000h]

SYSFSET is shown in Table 6-79.

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Internal. Only to be used through TI provided API.

Table 6-79 SYSFSET Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2FLAG2W0hInternal. Only to be used through TI provided API.
1FLAG1W0hInternal. Only to be used through TI provided API.
0FLAG0W0hInternal. Only to be used through TI provided API.

6.11.8 SYSFCLR Register (Offset = 24h) [Reset = 00000000h]

SYSFCLR is shown in Table 6-80.

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Internal. Only to be used through TI provided API.

Table 6-80 SYSFCLR Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2FLAG2W0hInternal. Only to be used through TI provided API.
1FLAG1W0hInternal. Only to be used through TI provided API.
0FLAG0W0hInternal. Only to be used through TI provided API.

6.11.9 SYSFSTA Register (Offset = 28h) [Reset = 00000000h]

SYSFSTA is shown in Table 6-81.

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Internal. Only to be used through TI provided API.

Table 6-81 SYSFSTA Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2FLAG2R0hInternal. Only to be used through TI provided API.
1FLAG1R0hInternal. Only to be used through TI provided API.
0FLAG0R0hInternal. Only to be used through TI provided API.

6.11.10 RSTCTL Register (Offset = 2Ch) [Reset = 00000000h]

RSTCTL is shown in Table 6-82.

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Reset Control Register.
This register configures and controls system reset.

Table 6-82 RSTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2LFLOSSR/W0hLF clock loss reset enable.
Trigger system reset when LF clock loss is detected, which reset the entire device and causes a reboot of the system.
The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to LFLOSSEV.
0h = LF clock loss detection will not trigger a system reset.
1h = LF clock loss detection will trigger a system reset.
1TSDENR/W0hTSD (Thermal Shutdown) enable.
TSD will trigger an immediate system reset, which reset the entire device and causes a reboot of the system.
The device will be in reset until released by the TSD IP.
The system reset event is captured as RSTSTA.TSDEV flag set.
0h = No effect
1h = Temperature shutdown comparator enable.
Note: If TSD IP not present, see DESCEX.TSD, enable will have no effect.
0SYSRSTR/W0hTrigger system reset, which will reset the entire device and causes a reboot of the system.
The system reset event is captured as RSTSTA.RESETSRC set to SYSRESET and RSTSTA.SYSSRC set to SYSRSTEV.
0h = No effect
1h = Trigger a system reset.

6.11.11 RSTSTA Register (Offset = 30h) [Reset = 00000000h]

RSTSTA is shown in Table 6-83.

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Reset Status.
This register contains the reset source and SHUTDOWN wakeup source for the system.
Check WUSTA.SRC first to ensure that wakeup from STANDBY is not set.
The capture feature is not rearmed until all of the possible reset sources have been released and the result has been copied to this register.
During the copy and rearm process it is one 24MHz period in which an eventual new system reset will be reported as Power on reset regardless of the root cause.

Table 6-83 RSTSTA Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17SDDETR0hWakeup from SHUTDOWN flag.
Note: This flag will be cleared when SLPCTL.SLPN is asserted.
0h = Wakeup from SHUTDOWN mode not triggered
1h = Wakeup from SHUTDOWN mode
16IOWUSDR0hWakeup from SHUTDOWN on an I/O event flag.
Note: This flag will be cleared when SLPCTL.SLPN is asserted.
0h = Wakeup from SHUTDOWN not triggered by an I/O event.
1h = Wakeup from SHUTDOWN triggered by an I/O event.
15-8RESERVEDR0hReserved
7-4SYSSRCR0hShows which reset event that triggered SYSRESET in RESETSRC
0h = LF clock loss event
1h = CPU reset event
2h = CPU LOCKUP event
3h = Watchdog timeout event
4h = System reset event
5h = Serial Wire Debug reset event
6h = Analog FSM timeout event
Eh = Analog Error reset event
Fh = Digital Error reset event
3TSDEVR0hSystem reset triggered by TSD event
0h = TSD event not triggered
1h = System reset triggered by TSD event
2-0RESETSRCR0hShows the root cause of the last system reset. More than one reported reset source can have been active during the last system reset, but only the root cause is reported.
If reset cause is SYSRESET or PINRESET, the other reset flags must be read to determine actual root cause.
0h = Power on reset
1h = Reset pin. TSD will also trigger a pin reset, so actual root cause is given by TSDEV reset flag status.
2h = Brown out detect on VDDS
4h = Brown out detect on VDDR
6h = Digital system reset. Actual root cause is given by SYSSRC.

6.11.12 BOOTSTA Register (Offset = 34h) [Reset = 00000000h]

BOOTSTA is shown in Table 6-84.

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Internal. Only to be used through TI provided API.

Table 6-84 BOOTSTA Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0hReserved
7-0FLAGR/W0hInternal. Only to be used through TI provided API.

6.11.13 AONRSTA1 Register (Offset = 3Ch) [Reset = 00000000h]

AONRSTA1 is shown in Table 6-85.

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AON Register Status 1.
This register contains the general purpose AON flags for SW, and is updated through AONRSET1.FLAG and AONRCLR1.FLAG.
The register is only reset on a POR event.

Table 6-85 AONRSTA1 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-0FLAGR0hState of the AON register flags

6.11.14 AONRSET1 Register (Offset = 40h) [Reset = 00000000h]

AONRSET1 is shown in Table 6-86.

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AON Register Set 1.
This register sets the AON flags that can be read through AONRSTA1.FLAG.

Table 6-86 AONRSET1 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0hReserved
17-0FLAGW0hWrite 1 to set AONRSTA1.FLAG
0h = No flags changed status
0003FFFFh = Set all flags

6.11.15 AONRCLR1 Register (Offset = 44h) [Reset = 00000000h]

AONRCLR1 is shown in Table 6-87.

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AON Register Clear 1.
This register clears the AON flags that can be read through AONRSTA1.FLAG.

Table 6-87 AONRCLR1 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR/W0hReserved
17-0FLAGW0hWrite 1 to clear AONRSTA1.FLAG
0h = No flags changed status
0003FFFFh = Clear all flags

6.11.16 ETPP Register (Offset = 64h) [Reset = 00000000h]

ETPP is shown in Table 6-88.

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Internal. Only to be used through TI provided API.

Table 6-88 ETPP Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

6.11.17 RETCFG0 Register (Offset = 7Ch) [Reset = 00000001h]

RETCFG0 is shown in Table 6-89.

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Internal. Only to be used through TI provided API.

Table 6-89 RETCFG0 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W1hInternal. Only to be used through TI provided API.

6.11.18 RETCFG1 Register (Offset = 80h) [Reset = 00000000h]

RETCFG1 is shown in Table 6-90.

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Internal. Only to be used through TI provided API.

Table 6-90 RETCFG1 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W0hInternal. Only to be used through TI provided API.

6.11.19 RETCFG2 Register (Offset = 84h) [Reset = 00000002h]

RETCFG2 is shown in Table 6-91.

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Internal. Only to be used through TI provided API.

Table 6-91 RETCFG2 Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0VALR/W2hInternal. Only to be used through TI provided API.

6.11.20 RETCFG3 Register (Offset = 88h) [Reset = 00000000h]

RETCFG3 is shown in Table 6-92.

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Internal. Only to be used through TI provided API.

Table 6-92 RETCFG3 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

6.11.21 RETCFG4 Register (Offset = 8Ch) [Reset = 00000000h]

RETCFG4 is shown in Table 6-93.

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Internal. Only to be used through TI provided API.

Table 6-93 RETCFG4 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

6.11.22 RETCFG5 Register (Offset = 90h) [Reset = 00000000h]

RETCFG5 is shown in Table 6-94.

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Internal. Only to be used through TI provided API.

Table 6-94 RETCFG5 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

6.11.23 RETCFG6 Register (Offset = 94h) [Reset = 00000000h]

RETCFG6 is shown in Table 6-95.

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Internal. Only to be used through TI provided API.

Table 6-95 RETCFG6 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved

6.11.24 RETCFG7 Register (Offset = 98h) [Reset = 00000000h]

RETCFG7 is shown in Table 6-96.

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Internal. Only to be used through TI provided API.

Table 6-96 RETCFG7 Register Field Descriptions
BitFieldTypeResetDescription
31-0RESERVEDR0hReserved