SWCU193 April 2023 CC2340R2 , CC2340R5 , CC2340R5-Q1
To save power, disable the ADC when not in use. The PWRDN bit in the CTL0 register selects the ADC power down policy between AUTO and MANUAL.
Configure PWRDN based on the max ADC sampling rate required and the operational needs in different power modes.
The reset value of PWRDN is ‘0’ which has the default behavior of automatic power down of the ADC peripheral at the end of a conversion and when the next sample signal is not required to be asserted immediately. When the PWRDN bit is set to ‘1’ the bit selects manual power down behavior. In this setting, the ADC is not powered down at the end of a conversion and remains enabled.
Refer to the device-specific data sheet for specifications on the ADC wakeup/enable time.