SBASAM0 March 2024 ADS127L18
ADVANCE INFORMATION
DCLK is the bit-clock output signal that shifts the data out. Channel data of DOUT are updated on the falling edge of DCLK and are latched by the host on the rising edge.
A programmable clock divider derives the DCLK signal frequency. If the DCLK signal frequency is not fast enough to transmit the channel data within a conversion period (FSYNC clock period), data are lost. Equation 22 derives the minimum DCLK signal frequency.
where:
Table 7-18 shows examples of CLK and DCLK signal frequency requirements. In the third row of the table, the data rate is 512kSPS in max-speed mode using four channels per DOUT pin and 24-bits per channel. The required DCLK signal frequency in this case is (512kSPS × 4 × 24) = 49.152MHz. The CLK input signal frequency is selected at 65.536MHz and dividing by 2 derives CLK = 32.768MHz for the ADC. The DCLK divider is programmed to 1, resulting in DCLK = 65.536MHz, which meets the minimum 49.152MHz. See the Clock Operation section for details of the clock dividers.
SPEED MODE | DATA RATE (kSPS) |
BITS PER DOUT PIN | DCLK MIN (MHz) |
CLK INPUT (MHZ) |
CLK DIVIDER | ADC CLOCK (MHz) |
DCLK DIVIDER | DCLK ACTUAL (MHz) |
---|---|---|---|---|---|---|---|---|
Max | 1365.3 | 48 (2 channels × 24 bits per channel) |
65.536 | 65.536 | 2 | 32.768 | 1 | 65.536 |
Max | 512 | 24 (1 channel × 24 bits per channel) |
12.288 | 32.768 | 1 | 32.768 | 2 | 16.384 |
Max | 512 | 96 (4 channels × 24 bits per channel) |
49.152 | 65.536 | 2 | 32.768 | 1 | 65.536 |
Max | 512 | 192 (8 channels × 24 bits per channel |
98.304 | 98.304 | 3 | 32.768 | 1 | 98.304 |
High | 1066.6 | 96 (4 channels × 24 bits per channel) |
102.4 | 102.4 | 4 | 25.6 | 1 | 102.4 |
Mid | 200 | 160 (4 channels × 40 bits per channel) |
32.0 | 38.4 | 3 | 12.8 | 1 | 38.4 |
Low | 50 | 320 (8 channels × 40 bits per channel) |
16.0 | 25.6 | 8 | 3.2 | 1 | 25.6 |
When operating two or more devices in daisy-chain mode, the maximum DCLK signal frequency is shown in the Specifications section.