SBASAM0 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9.1 Sinc4 Filter

The sinc4 filter performs averaging and decimation of the modulator data for data rates ranging to 1365.3kSPS in max-speed mode and to 133.333 kSPS in low-speed mode. Increasing the OSR value decreases the ADC data rate and simultaneously reduces signal bandwidth and total noise resulting from increased decimation and data averaging.

The amount of data averaging is reduced for OSR values equal to 12, 16, and 24. Because of this reduction, full 24-bit output data resolution is not available. Table 7-5 summarizes the output data resolution for these OSR values.

Table 7-5 Sinc4 Data Resolution
OSR RESOLUTION (Bits)
12 19
16 20
24 23
≥32 24

Table 7-18 lists the sinc4 filter characteristics.

Table 7-6 Sinc4 Filter Characteristics
MODE fCLK (MHz) OSR DATA RATE (kSPS) –3-dB FREQUENCY (kHz) LATENCY TIME (μs)
Max speed 32.768 12 1365.3 310.2 3.30
High speed 25.6 1066.6 242.3 4.38
Mid speed 12.8 533.3
 121.2 8.75
Low speed 3.2 133.33 30.3 35
Max speed 32.768 16 1024 232.7 4.27
High speed 25.6 800 181.8 5.63
Mid speed 12.8 400 90.9 11.3
Low speed 3.2 100 22.7 45
Max speed 32.768 24 682.67 155.1 6.23
High speed 25.6 533.3 121.2 8.13
Mid speed 12.8 266.67 60.6 16.3
Low speed 3.2 66.67 15.1 65
Max speed 32.768 32 512 116.3 8.18
High speed 25.6 400 90.9 10.6
Mid speed 12.8 200 45.4 21.3
Low speed 3.2 50 11.4 85
Max speed 32.768 64 256 58.2 16.0
High speed 25.6 200 45.4 20.6
Mid speed 12.8 100 22.7 41.3
Low speed 3.2 25 5.68 165
Max speed 32.768 128 128 29.1 31.6
High speed 25.6 100 22.7 40.6
Mid speed 12.8 50 11.4 81.3
Low speed 3.2 12.5 2.84 325
Max speed 32.768 256 64 14.5 62.9
High speed 25.6 50 11.4 80.6
Mid speed 12.8 25 5.68 161
Low speed 3.2 6.25 1.42 645
Max speed 32.768 512 32 7.27 125
High speed 25.6 25 5.68 161
Mid speed 12.8 12.5 2.84 321
Low speed 3.2 3.125 0.710 1285
Max speed 32.768 1024 16 3.64 250
High speed 25.6 12.5 2.84 321
Mid speed 12.8 6.25 1.42 641
Low speed 3.2 1.5625 0.355 2565
Max speed 32.768 2048 8 1.82 500
High speed 25.6 6.25 1.42 641
Mid speed 12.8 3.125 0.710 1281
Low speed 3.2 0.7813 0.178 5125
Max speed 32.768 4096 4 0.909 1000
High speed 25.6 3.125 0.710 1281
Mid speed 12.8 1.563 0.355 2561
Low speed 3.2 0.391 0.089 10245

Figure 7-18 and Figure 7-19 show the sinc4 filter frequency response at OSR = 32. The frequency response consists of a series of response nulls occurring at discrete frequencies. These null frequencies occur at multiples of fDATA. At the null frequencies, the filter has zero gain. A folded image of the overall frequency response appears at multiples of fMOD, as illustrated in the frequency plot of Figure 7-19. Attenuation is not provided by the filter at input frequencies near n × fMOD (n = 1, 2, 3, and so on). If present at these frequencies, aliases occurs in the pass band.

GUID-20201006-CA0I-VDBF-P30Z-ZTLM55Q8WJQW-low.gifFigure 7-18 Sinc4 Frequency Response
(OSR = 32)
GUID-20201006-CA0I-Q0SJ-N9TB-N7CKR6R5TSKS-low.gifFigure 7-19 Sinc4 Frequency Response to fMOD (OSR = 32)