SBASAM0 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

GUID-20220930-SS0I-GHBZ-0GHK-JWBP90H57Z8D-low.svg Figure 4-1 ADS127L14 RSH Package, 56-Pin VQFN (Top View)
GUID-20220930-SS0I-5KRX-W0V4-T9XT9PBPL9C1-low.svg Figure 4-2 ADS127L18 RSH Package, 56-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME ADS127L14 ADS127L18
AINN0 42 44 I Channel 0 negative analog input. See the Analog Inputs section for details.
AINN1 38 42 I Channel 1 negative analog input. See the Analog Inputs section for details.
AINN2 34 40 I Channel 2 negative analog input. See the Analog Inputs section for details.
AINN3 30 38 I Channel 3 negative analog input. See the Analog Inputs section for details.
AINN4 –- 36 I Channel 4 negative analog input. See the Analog Inputs section for details.
AINN5 –- 34 I Channel 5 negative analog input. See the Analog Inputs section for details.
AINN6 –- 32 I Channel 6 negative analog input. See the Analog Inputs section for details.
AINN7 –- 30 I Channel 7 negative analog input. See the Analog Inputs section for details.
AINP0 41 43 I Channel 0 positive analog input. See the Analog Inputs section for details.
AINP1 37 41 I Channel 1 positive analog input. See the Analog Inputs section for details.
AINP2 33 39 I Channel 2 positive analog input. See the Analog Inputs section for details.
AINP3 29 37 I Channel 3 positive analog input. See the Analog Inputs section for details.
AINP4 –- 35 I Channel 4 positive analog input. See the Analog Inputs section for details.
AINP5 –- 33 I Channel 5 positive analog input. See the Analog Inputs section for details.
AINP6 –- 31 I Channel 6 positive analog input. See the Analog Inputs section for details.
AINP7 –- 29 I Channel 7 positive analog input. See the Analog Inputs section for details.
AVDD1 23, 24 23, 24 P Positive analog supply 1. See the Power Supplies section for details.
AVDD2 25 25 P Positive analog supply 2. See the Power Supplies section for details.
AVSS 22, 28, 31, 32, 35, 36, 39, 40, 43, 44, 45, 51 22, 28, 45, 51 P Negative analog supply. See the Power Supplies section for details.
CAPA 26, 27 26, 27 P Analog voltage regulator output bypass. See the CAPA and CAPD section for details.
CAPD 20 20 P Digital voltage regulator output bypass. See the CAPA and CAPD section for details.
CLKIN 16 16 I Clock input. See the Clock Operation section for details.
CS/SPEED 55 55 I SPI mode: Active-low chip select. See the SPI Programming section for details.
Hardware mode (tri-state input): Speed range select.
See the Hardware Programming section for details.
DCLK 14 14 O Frame-sync bit clock output. See the Frame-Sync Data Port section for details.
DGND 17, 21 17, 21 GND Digital ground.
DOUT0 6 6 O Data output 0. See the Frame-Sync Data Port section for details.
DOUT1 7 7 O Data output 1. See the Frame-Sync Data Port section for details.
DOUT2/GPIO2 8 8 I/O Data output 2. See the Frame-Sync Data Port section for details.
General-purpose input-output 2. See the GPIO section for details.
DOUT3/GPIO3 9 9 I/O Data output 3. See the Frame-Sync Data Port section for details.
General-purpose input-output 3. See the GPIO section for details.
DOUT4/DIN3/GPIO4 –- 10 I/O Data output 4 and daisy-chain data input 3. See the Frame-Sync Data Port section for details.
General-purpose input-output 4. See the GPIO section for details.
DOUT5/DIN2/GPIO5 –- 11 I/O Data output 5 and daisy-chain data input 2. See the Frame-Sync Data Port section for details.
General-purpose input-output 5. See the GPIO section for details.
DOUT6/DIN1/GPIO6 –- 12 I/O Data output 6 and daisy-chain data input 1. See the Frame-Sync Data Port section for details.
General-purpose input-output 6. See the GPIO section for details.
DOUT7/DIN0/GPIO7 –- 13 I/O Data output 7 and daisy-chain data input 0. See the Frame-Sync Data Port section for details.
General-purpose input-output 7. See the GPIO section for details.
DIN3/GPIO4 10 –- I/O Daisy-chain data input 3. See the Frame-Sync Data Port section for details.
General-purpose input-output 4. See the GPIO section for details.
DIN2/GPIO5 11 –- I/O Daisy-chain data input 2. See the Frame-Sync Data Port section for details.
General-purpose input-output 5. See the GPIO section for details.
DIN1/GPIO6 12 –- I/O Daisy-chain data input 1. See the Frame-Sync Data Port section for details.
General-purpose input-output 6. See the GPIO section for details.
DIN0/GPIO7 13 –- I/O Daisy-chain data input 0. See the Frame-Sync Data Port section for details.
General-purpose input-output 7. See the GPIO section for details.
ERROR 5 5 O Open-drain output error signal. See the ERROR Pin and ERR_FLAG Bit section for details.
FSYNC 15 15 O Frame-sync word clock output. See the Frame-Sync Data Port section for details.
GPIO0/TDM 3 3 I/O General purpose input-output 0. See the GPIO section for details.
Hardware mode (tri-state input): TDM ratio select.
See the Hardware Programming section for details.
GPIO1/HDR 4 4 I/O General purpose input-output 1. See the GPIO section for details.
Hardware mode (tri-state input): Data header select.
See the Hardware Programming section for details.
IOVDD 18, 19 18, 19 P Digital I/O supply voltage. See the Power Supplies section for details.
MODE 54 54 I Tri-state input.
Configuration mode select:
1 = SPI program mode
0 or float = Hardware program mode
REFN 47, 48 47, 48 I Negative reference voltage input. See the Reference Voltage section for details.
REFP 49, 50 49, 50 I Positive reference voltage input. See the Reference Voltage section for details.
RESET 52 52 I Reset input, active low. See the RESET Pin section for details.
SCLK/FLTR 56 56 I SPI mode: Serial clock input. See the SPI Programming section for details.
Hardware mode (tri-state input): Filter mode select.
See the Hardware Programming section for details.
SDI/OSR0 1 1 I SPI mode: Serial data input. See the SPI Programming section for details.
Hardware mode (tri-state input): Filter OSR0 select.
See the Hardware Programming section for details.
SDO/OSR1 2 2 I/O SPI mode: Serial data output. See the SPI Programming section for details.
Hardware mode (tri-state input): Filter OSR1 select.
See the Hardware Programming section for details.
START 53 53 I Conversion control. See the Synchronization section for details.
VCM 46 46 O Common-mode voltage output. See the VCM Output Voltage section for details.
Thermal Pad — Thermal power pad. Connect this pad to AVSS.
(1) I = input, O = output, I/O = bidirectional input-output, P = power, GND = ground.