SBASAM0 March 2024 ADS127L18
ADVANCE INFORMATION
When operating the data port at high switching frequencies (75MHz to 100MHz), a DOUT offset timing adjustment is provided to help meet external timing requirements. The offset timing delays or advances the DOUT signals relative to the FSYNC and DCLK signals. The total offset range is ±6ns, relative to the nominal DOUT timing shown in the Switching Characteristics. Figure 7-39 shows the offset timing operation. The timing between the FSYNC and DCLK signals is fixed. The signed-magnitude DOUT_DLY[4:0] bits, located in the DP_CFG2 register, control the offset timing.