SBASAM0 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C; all specifications are at AVDD1 =  5V, AVDD2 = 1.8V to 5V, AVSS = 0V, IOVDD = 1.8V, VIN = 0V, VCM = 2.5V, VREFP =  4.096V, VREFN = 0V, high-reference range, 1x input range, all speed modes, all channels active, input precharge buffers on, and reference precharge buffer on (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS, MAX-SPEED MODE
Input current,
differential input voltage		 Input buffers off 125 µA/V
Input buffers off, 2x input range 60
Input buffers on ±4 µA
Input current drift,
differential input voltage		 Input buffers off 5 nA/V/°C
Input buffers off, 2x input range 2
Input buffers on 20 nA/°C
Input current,
common-mode input voltage		 Input buffers off 6.5 µA/V
Input buffers off, 2x input range 3
Input buffers on ±4 µA
ANALOG INPUTS, HIGH-SPEED MODE
Input current,
differential input voltage		 Input buffers off 95 µA/V
Input buffers off, 2x input range 47
Input buffers on ±3 µA
Input current drift,
differential input voltage		 Input buffers off 3 nA/V/°C
Input buffers off, 2x input range 1.5
Input buffers on 5 nA/°C
Input current,
common-mode input voltage		 Input buffers off 5 µA/V
Input buffers off, 2x input range 2.5
Input buffers on ±3 µA
ANALOG INPUTS, MID-SPEED MODE
Input current,
differential input voltage		 Input buffers off 47 µA/V
Input buffers off, 2x input range 25
Input buffers on ±1.5 µA
Input current drift,
differential input voltage		 Input buffers off 2 nA/V/°C
Input buffers off, 2x input range 1
Input buffers on 5 nA/°C
Input current,
common-mode input voltage		 Input buffers off 2.5 µA/V
Input buffers off, 2x input range 1.3
Input buffers on ±1.5 µA
ANALOG INPUTS, LOW-SPEED MODE
Input current,
differential input voltage		 Input buffers off 12 µA/V
Input buffers off, 2x input range 6
Input buffers on ±0.4 µA
Input current drift,
differential input voltage		 Input buffers off 1 nA/V/°C
Input buffers off, 2x input range 0.5
Input buffers on 0.2 nA/°C
Input current,
common-mode input voltage		 Input buffers off 0.6 µA/V
Input buffers off, 2x input range 0.3
Input buffers on ±0.4 µA
DC PERFORMANCE
Resolution OSR ≥ 32 24 Bits
Noise See the Noise Performance section for details
INL Integral nonlinearity (1) TA = 25°C ± 5°C 0.4 TBD ppm of FSR
TA = 0°C to 70°C 0.4 TBD
TA = –40°C to 125°C 0.4 TBD
Max-speed mode 1.5
Offset error TA = 25°C –250 ±30 250 µV
Offset drift 50 200 nV/°C
Gain error TA = 25°C –2500 ±200 2500 ppm of FSR
Gain drift 0.5 1.0 ppm of FSR/°C
NMRR Normal-mode rejection ratio fIN = 50Hz (±1Hz), fDATA = 50SPS 100 dB
fIN = 60Hz (±1Hz), fDATA = 60SPS 100
CMRR Common-mode rejection ratio At dc 110 130 dB
Up to 10kHz 115
At dc, 2x input range 95
PSRR Power-supply rejection ratio AVDD1, dc 100 120 dB
AVDD2, dc 115 130
IOVDD, dc 115 130
AC PERFORMANCE, MAX-SPEED MODE
fDATA Data rate Wideband filter 4 512 kSPS
Low-latency filter 0.1024 1365.3 kSPS
Crosstalk fIN = 1kHz, VIN = –0.2dbFS (3) -120 dB
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 256kSPS		 Wideband filter 109 111.5 dB
Wideband filter,
VREF = 2.5V		 107.5
Wideband filter,
VREF = 2.5V,
2x input range		 108.5
Low-latency filter 112 114
Low-latency filter,
VREF = 2.5V		 110.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 256kSPS
 		 Wideband filter 110 dB
Wideband filter,
VREF  = 2.5V		 106
Wideband filter,
VREF  = 2.5V,
2x input range		 107
Low-latency filter 112
Low-latency filter,
VREF = 2.5V		 108.5
Low-latency filter
VREF = 2.5V,
2x input range		 110
THD Total harmonic distortion fIN =  1kHz,
VIN = –0.2dBFS,
OSR = 64, 
fDATA = 200kSPS,
9 harmonics		 VREF = 2.5V –119 TBD dB
VREF = 4.096V –110 TBD dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz,
VIN = –6.5dBFS		 Second-order terms –120 dB
Third-order terms –120
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 110 dB
Phase match Channel to channel, fIN = 200kHz 0.25 TBD ns
AC PERFORMANCE, HIGH-SPEED MODE
fDATA Data rate Wideband filter 3.125 400 kSPS
Low-latency filter 0.08 1067
Crosstalk fIN = 1kHz, VIN = –0.2dBFS (3) -130 dB
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 200kSPS		 Wideband filter 109 111.5 dB
Wideband filter,
VREF = 2.5V		 107.5
Wideband filter,
VREF = 2.5V,
2x input range		 108.5
Low-latency filter 112 114
Low-latency filter,
VREF = 2.5V		 110.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 200kSPS
 		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5V		 106
Wideband filter,
VREF = 2.5V,
2x input range		 107
Low-latency filter 112
Low-latency filter,
VREF = 2.5V		 108.5
Low-latency filter,
VREF = 2.5V,
2x input range		 110
THD Total harmonic distortion
fIN =  1kHz,
VIN = –0.2dBFS,
OSR = 64, 
fDATA = 200kSPS,
9 harmonics		 VREF = 2.5V –125 TBD dB
VREF = 4.096V –125 TBD dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz, VIN =  –6.5dBFS Second-order terms –125 dB
Third-order terms –125 dB
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 125 dB
Phase match Channel to channel, fIN = 160kHz 0.25 TBD ns
AC PERFORMANCE, MID-SPEED MODE
fDATA Data rate Wideband filter 1.5625 200 kSPS
Low-latency filter 0.08 533.3
Crosstalk fIN = 1kHz, VIN = –0.2dBFS(3) -135 dB
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 100kSPS		 Wideband filter 109 111.5 dB
Wideband filter,
VREF = 2.5V		 107.5
Wideband filter,
VREF = 2.5V
2x input range		 108.5
Low-latency filter 112 114
Low-latency filter,
VREF = 2.5V		 110.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dbFS,
OSR = 64,
fDATA = 100kSPS
 		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5V		 106
Wideband filter,
VREF = 2.5V,
2x input range		 107
Low-latency filter 112
Low-latency filter,
VREF = 2.5V		 108.5
Low-latency filter,
VREF = 2.5V,
2x input range		 110
THD Total harmonic distortion fIN =  1kHz,
VIN = –0.2dBFS,
OSR = 64, 
fDATA = 200kSPS,
9 harmonics		 VREF = 2.5V –125 TBD dB
VREF = 4.096V –125 TBD dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz, VIN = –6.5dbFS Second-order terms –125 dB
Third-order terms –125
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = -0.2dbFS, OSR = 64 125 dB
Phase match Channel to channel, fIN = 80kHz 0.25 TBD ns
AC PERFORMANCE, LOW-SPEED MODE
fDATA Data rate Wideband filter 0.390625 50 kSPS
Low-latency filter 0.01 133.3
Crosstalk fIN = 1kHz, VIN = –0.2dBFS (3) -135 dB
DR Dynamic range Inputs shorted,
OSR = 64,
fDATA = 25kSPS		 Wideband filter 109 112 dB
Wideband filter,
VREF = 2.5V		 107.5
Wideband filter,
VREF = 2.5V,
2x input range		 108.5
Low-latency filter 111.5 114.5
Low-latency filter,
VREF = 2.5V		 110.5
Low-latency filter,
VREF = 2.5V,
2x input range		 111.5
SNR Signal-to-noise ratio fIN = 1kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 25kSPS		 Wideband filter 110 dB
Wideband filter,
VREF = 2.5V		 106
Wideband filter,
VREF = 2.5V,
2x input range		 108
Low-latency filter 112
Low-latency filter,
VREF = 2.5V		 108
Low-latency filter,
VREF = 2.5V,
2x input range		 110
THD Total harmonic distortion fIN = 1 kHz,
VIN = –0.2dBFS,
OSR = 64,
fDATA = 25kSPS,
9 harmonics		 VREF = 2.5V –125 TBD dB
VREF = 4.096V –125 TBD dB
IMD Intermodulation distortion fIN = 9.7kHz and 10.3kHz, VIN = –6.5dBFS Second-order terms –125 dB
Third-order terms –125 dB
SFDR Spurious-free dynamic range fIN = 1kHz, VIN = –0.2dBFS, OSR = 64 125 dB
Phase match Channel to channel, fIN = 20kHz 0.25 TBD ns
WIDEBAND FILTER CHARACTERISTICS
Pass-band frequency Within envelope of pass-band ripple 0.4 ∙ fDATA Hz
–0.1dB frequency 0.4125 ∙ fDATA
–3dB frequency 0.4374 ∙ fDATA
Pass-band ripple –0.0004 0.0004 dB
Stop-band frequency At stop-band attenuation 0.5 · fDATA Hz
Stop-band attenuation (2) 106 dB
Group delay 34 / fDATA s
Settling time 68 / fDATA s
VOLTAGE REFERENCE INPUTS
REFP and REFN input current REFP buffer off Max-speed mode 225 µA/V/ch
High-speed mode 190
Mid-speed mode 130
Low-speed mode 80
REFP input current REFP buffer on ±2 µA/ch
REFP and REFN
input current drift		 REFP buffer off Max-speed mode 10 nA/℃/ch
High-speed mode 10
Mid-speed mode 10
Low-speed mode 10
REFP input current drift REFP buffer on 10 nA/℃/ch
INTERNAL OSCILLATOR
f(OSC) Oscillator frequency 25.4 25.6 25.8 MHz
VCM OUTPUT VOLTAGE
Output voltage (AVDD1 + AVSS) / 2 V
Accuracy –1% ±0.1% 1%
Voltage noise 1kHz bandwidth 25 µVRMS
Start-up time CL = 100nF 1 ms
Capacitive load 100 nF
Resistive load 2 kΩ
Short-circuit current limit 10 mA
DIGITAL INPUTS/OUTPUTS
VOL Logic-low output level OUT_DRV = 0b, IOL = 2mA 0.2 ∙ IOVDD V
OUT_DRV = 1b, IOL = 1mA 0.2 ∙ IOVDD
VOH Logic-high output level OUT_DRV = 0b, IOH = –2mA 0.8 ∙ IOVDD V
OUT_DRV = 1b, IOH = –1mA 0.8 ∙ IOVDD
Input hysteresis 150 mV
Input current –1 1 µA
ANALOG SUPPLY CURRENT
IAVDD1, IAVSS AVDD1, AVSS current
(buffers off)		 One active channel Max-speed mode 3.4 3.7 mA
Each additional channel 1.5 1.7 mA/ch
One active channel High-speed mode 3.0 3.3 mA
Each additional channel 1.2 1.3 mA/ch
One active channel Mid-speed mode 2.2 2.5 mA
Each additional channel 0.5 0.6 mA/ch
1 or 8 active channels Low-speed mode 1.7 1.9 mA
Standby mode 35 µA/ch
Power-down mode 5
AVDD1, AVSS buffer current Input buffers Max-speed mode 1.75 2.3 mA/buffer
High-speed mode 1.35 1.9
Mid-speed mode 0.7 1.0
Low-speed mode 0.2 0.3
REFP buffers Max-speed mode 1.8 2.0 mA/buffer
High-speed mode 1.5 1.6
Mid-speed mode 1 1.1
Low-speed mode 0.4 0.5
VCM buffer 0.1 mA
IAVDD2, IAVSS AVDD2, AVSS current Max-speed mode 4.5 4.9 mA/ch
High-speed mode 3.5 3.8
Mid-speed mode 2.2 2.4
Low-speed mode 0.85 0.95
Standby mode 60 µA/ch
Power-down mode 1
DIGITAL SUPPLY CURRENT
IIOVDD IOVDD current Wideband filter
OSR = 32		 Max-speed mode 2.7 3.4 mA/ch
High-speed mode 2.1 2.7
Mid-speed mode 1.0 1.4
Low-speed mode 0.3 0.4
Low-latency filter
OSR = 32		 Max-speed mode 0.8 1.2
High-speed mode 0.6 1
Mid-speed mode 0.45 0.6
Low-speed mode 0.15 0.2
Standby mode External clock 10 µA/ch
Internal oscillator 40
Power-down mode 10
POWER DISSIPATION
PD Power dissipation
(all channels active)		 ADS127L14
wideband filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 91 104 mW
High-speed mode 73 83
Mid-speed mode 42 49
Low-speed mode 17 19
ADS127L14
low-latency filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 78 88
High-speed mode 63 71
Mid-speed mode 38 43
Low-speed mode 16 18
ADS127L18
wideband filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 173 198 mW
High-speed mode 138 156
Mid-speed mode 75 88
Low-speed mode 25 29
ADS127L18
low-latency filter,
AVDD2 = 1.8V,
buffers off		 Max-speed mode 146 166
High-speed mode 116 131
Mid-speed mode 67 77
Low-speed mode 23 26
(1) Best-fit method.
(2) Stop-band attenuation as provided by the digital filter. Input frequencies in the stop band intermodulate with the chop frequency beginning at fMOD / 32, which results in stop-band attenuation <106dB. See the Stop-Band Attenuation figure for details.
(3) Crosstalk with three (ADS127L14) or seven (ADS127L18) full-scale input channels coupling to one zero input channel.