SBASAM0 March   2024 ADS127L18

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Internal Oscillator
        2. 7.3.3.2 External Clock
      4. 7.3.4 Power Supplies
        1. 7.3.4.1 AVDD1 and AVSS
        2. 7.3.4.2 AVDD2
        3. 7.3.4.3 IOVDD
        4. 7.3.4.4 Power-On Reset (POR)
        5. 7.3.4.5 CAPA and CAPD
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
      9. 7.3.9 Low-Latency Filter (Sinc)
        1. 7.3.9.1 Sinc4 Filter
        2. 7.3.9.2 Sinc4 + Sinc1 Cascade Filter
        3. 7.3.9.3 Sinc3 Filter
        4. 7.3.9.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1  Speed Modes
      2. 7.4.2  Synchronization
        1. 7.4.2.1 Synchronized Control Mode
        2. 7.4.2.2 Start/Stop Control Mode
      3. 7.4.3  Digital Filter Settling
      4. 7.4.4  Conversion-Start Delay Time
      5. 7.4.5  Data Averaging
      6. 7.4.6  Calibration
        1. 7.4.6.1 Offset Calibration Registers
        2. 7.4.6.2 Gain Calibration Registers
        3. 7.4.6.3 Calibration Procedure
      7. 7.4.7  Reset
        1. 7.4.7.1 RESET Pin
        2. 7.4.7.2 Reset by SPI Register
        3. 7.4.7.3 Reset by SPI Input Pattern
      8. 7.4.8  Power-Down
      9. 7.4.9  Idle and Standby Modes
      10. 7.4.10 Diagnostics
        1. 7.4.10.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.10.2 Clock Counter
        3. 7.4.10.3 SCLK Counter
        4. 7.4.10.4 Frame-Sync CRC
        5. 7.4.10.5 SPI CRC
        6. 7.4.10.6 Register Map CRC
        7. 7.4.10.7 Self Test
      11. 7.4.11 Frame-Sync Data Port
        1. 7.4.11.1 FSYNC Pin
        2. 7.4.11.2 DCLK Pin
        3. 7.4.11.3 DOUTn Pins
        4. 7.4.11.4 DINn Pins
        5. 7.4.11.5 Time Division Multiplexing (TDM)
        6. 7.4.11.6 Data Size
        7. 7.4.11.7 STATUS_DP Header
        8. 7.4.11.8 Daisy Chain
        9. 7.4.11.9 Data Port Offset Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 SPI Commands
        1. 7.5.4.1 Read Register Command
        2. 7.5.4.2 Write Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Antialias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.9.2 Sinc4 + Sinc1 Cascade Filter

The sinc4 + sinc1 filter is the cascade of a sinc4 and a sinc1 filter section. The fixed OSR = 32 of the sinc4 stage multiplied by the programmable OSR of the sinc1 stage determines the ADC output data rate. The sinc4 + sinc1 filter mode has comparably less latency time than that of the single-stage sinc4 filter. Table 7-7 summarizes the sinc4 + sinc1 filter characteristics.

Table 7-7 Sinc4 + Sinc1 Cascade Filter Characteristics
MODE fCLK
(MHz)		 OSR
(A × B)2		 DATA RATE
(kSPS)		 –3dB FREQUENCY
(kHz)		 LATENCY TIME
(µs)1
Max speed 32.768 64
(32 × 2)		 256 87.49 10.26
High speed 25.6 200 68.35 13.13
Mid speed 12.8 100 34.18 26.26
Low speed 3.2 25 8.544 105.04
Max speed 32.768 128
(32 × 4)		 128 52.44 14.16
High speed 25.6 100 40.97 18.13
Mid speed 12.8 50 20.49 36.26
Low speed 3.2 12.5 5.121 145.04
Max speed 32.768 320
(32 × 10)		 51.2 22.36 25.88
High speed 25.6 40 17.47 33.13
Mid speed 12.8 20 8.735 66.26
Low speed 3.2 5 2.184 265.04
Max speed 32.768 640
(32 × 20)		 25.6 11.28 45.41
High speed 25.6 20 8.814 58.13
Mid speed 12.8 10 4.407 116.26
Low speed 3.2 2.5 1.102 465.04
Max speed 32.768 1280
(32 × 40)		 12.8 5.658 84.48
High speed 25.6 10 4.420 108.13
Mid speed 12.8 5 2.210 216.26
Low speed 3.2 1.25 0.552 865.04
Max speed 32.768 3200
(32 × 100)		 5.12 2.266 201.66
High speed 25.6 4 1.770 258.13
Mid speed 12.8 2 0.885 516.26
Low speed 3.2 0.5 0.221 2065.0
Max speed 32.768 6400
(32 × 200)		 2.56 1.133 396.98
High speed 25.6 2 0.885 508.13
Mid speed 12.8 1 0.443 1016.26
Low speed 3.2 0.25 0.111 4065.04
Max speed 32.768 12800
(32 × 400)		 1.28 0.566 787.60
High speed 25.6 1 0.442 1008.13
Mid speed 12.8 0.5 0.221 2016.26
Low speed 3.2 0.125 0.055 8065.04
Max speed 32.768 32000
(32 × 1000)		 0.512 0.226 1959.47
High speed 25.6 0.4 0.177 2508.13
Mid speed 12.8 0.2 0.089 5016.26
Low speed 3.2 0.05 0.022 20065.04
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.
(2) A = First stage OSR, B = Second stage OSR.

Figure 7-20 illustrates the frequency response of the sinc4 + sinc1 filter for three OSR values. The combined frequency response is the overlay response of the sinc1 filter to the sinc4 filter. For low values of OSR, the response profile is dominated by the rolloff of the sinc4 filter. Nulls in the frequency response occur at n · fDATA, n = 1, 2, 3, and so on. At the null frequencies, the filter has zero gain.

GUID-20211020-SS0I-S41P-BSWJ-DSVMZP2HHBD2-low.svg Figure 7-20 Sinc4 + Sinc1 Frequency Response