SBAS949A February 2020 – February 2021 ADS131M06
The device provides conversion data for each channel at the data rate. The time when data are available relative to DRDY asserting is determined by the channel phase calibration setting and the DRDY_SEL[1:0] bits in the MODE register when in continuous-conversion mode. All data are available immediately following DRDY assertion in global-chop mode. The conversion status of all channels is available as the DRDY[5:0] bits in the STATUS register. The STATUS register content is automatically output as the response to the NULL command.
Conversion data are 24 bits. The data LSBs are truncated when the device operates with a 16-bit word size. The LSBs are zero padded or the MSBs sign extended when operating with a 32-bit word size depending on the setting of the WLENGTH[1:0] bits in the MODE register.
Data are given in binary two's complement format. Use Equation 10 to calculate the size of one code (LSB).
A positive full-scale input VIN ≥ +FSR – 1 LSB = 1.2 / Gain – 1 LSB produces an output code of 7FFFFFh and a negative full-scale input (VIN ≤ –FSR = –1.2 / Gain) produces an output code of 800000h. The output clips at these codes for signals that exceed full-scale.
Table 8-10 summarizes the ideal output codes for different input signals.
VIN = VAINP – VAINN
|IDEAL OUTPUT CODE|
|≥ FSR (223 – 1) / 223||7FFFFFh|
|FSR / 223||000001h|
|–FSR / 223||FFFFFFh|
Figure 8-19 shows the mapping of the analog input signal to the output codes.