SLASE67A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
The ADS54J54 has an input bandwidth of approximately 900 MHz, but we will consider an application involving the first or second Nyquist zones, so we will limit the frequency bandwidth here to be under 250 MHz. We will also consider a 50-ohm signal source, so the proper termination would be 50-Ω differential. As seen in Figure 104 and Figure 105, the input impedance of the analog input at 250 MHz is large compared to 50 Ω, so the proper termination can be 50-Ω differential as shown in Figure 101. Splitting the termination into two 25-Ω resistors with an AC capacitor to ground provides a path to filter out any ripple on the common mode that may result from any amplitude or phase imbalance of the differential input, improving SFDR performance. The ADS54J54 provides a VCM output that may be used to bias the input to the desired level, but as seen in Figure 67 the signal is internally biased inside the ADC so an external biasing to VCM is not required. If an external biasing to VCM were to be employed, the VCM voltage may be applied to the mid-point of the two 25-Ω termination resistors in Figure 101.
For the clock input, Figure 103 shows the SNR of the device above 100 MHz begins to degrade with external clock jitter of greater than 100 fs rms, so we will recommend the clock source be limited to approximately 100 fS of rms jitter. For the ADS54J54 EVM, the LMK04828 clock device is capable of providing a low-jitter sample clock as well as providing the SYSREF signal required as shown in Figure 62 and Figure 63, so that clocking device is one good choice for the clocking solution for the ADS54J54.