Quad-Channel, 14-Bit, 500-MSPS Analog-to-Digital Converter (ADC)


Product details


Sample rate (Max) (MSPS) 500 Resolution (Bits) 14 Number of input channels 4 Interface type JESD204B Analog input BW (MHz) 900 Features High Performance Rating Catalog Input range (Vp-p) 1.25 Power consumption (Typ) (mW) 3500 Architecture Pipeline SNR (dB) 68.3 ENOB (Bits) 11 SFDR (dB) 95 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFN (RGC) 64 81 mm² 9 x 9 open-in-new Find other High-speed ADCs (>10MSPS)


  • 4 Channel, 14-Bit 500 MSPS ADC
  • Analog input buffer with high impedance input
  • Flexible input clock buffer with divide by 1/2/4
  • 1.25 VPP Differential full-scale input
  • JESD204B Serial interface
    • Subclass 1 compliant up to 5 Gbps
    • 1 Lane Per ADC up to 250 Msps
    • 2 Lanes Per ADC up to 500 Msps
  • 64-Pin QFN Package (9 mm x 9 mm)
  • Key specifications:
    • Power dissipation: 875 mW/ch
    • Input bandwidth (3 dB): 900 MHz
    • Aperture jitter: 98 fs rms
    • Channel isolation: 85 dB
    • Performance at ƒin = 170 MHz at 1.25 VPP,
      1lane 2x Decimation –1 dBFS
      • SNR: 67.2 dBFS
      • SFDR: 85 dBc HD2,3; 95 dBFS non-HD2,3
    • Performance at ƒin = 370 MHz at 1.25 VPP,
      2lane no Decimation –1 dBFS
      • SNR: 64.7 dBFS
      • SFDR: 75 dBc HD2,3; 83 dBFS non-HD2,3
open-in-new Find other High-speed ADCs (>10MSPS)


The ADS54J54 is a low power, wide bandwidth 14-bit 500 MSPS quad channel analog-to-digital converter (ADC). It supports the JESD204B serial interface with data rates up to 5 Gbps supporting 1 or 2 lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. A sampling clock divider allows more flexibility for system clock architecture design. The ADS54J54 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption. Optional 2x Decimation Filter provides high-pass or low-pass filter modes.

open-in-new Find other High-speed ADCs (>10MSPS)

Technical documentation

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Type Title Date
* Data sheet ADS54J54 Quad Channel 14-Bit 500 MSPS ADC datasheet (Rev. A) Aug. 01, 2019
Technical article Keys to quick success using high-speed data converters Oct. 13, 2020
Technical article How to achieve fast frequency hopping Mar. 03, 2019
Selection guide TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
Technical article RF sampling: Learning more about latency Feb. 09, 2017
Technical article Why phase noise matters in RF sampling converters Nov. 28, 2016
User guide ADS54J54 EVM Users Guide (Rev. A) Jan. 08, 2016
User guide Pipeline ADC Code Error Rate Analysis and Measurement Nov. 03, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The ADS54J54 EVM demonstrates the performance of a quad 500Msps 14 bit ADC with the JESD204B interface. It includes the ADS54J54 device and JESD204B clocking is provided by the LMK04828 and TI voltage regulators to provide the necessary voltages. The input for each channel of the ADC is by default (...)

  • Flexible input clock buffer with 1/2/4 divider to simplify clocking
  • On chip dither to improve SFDR
  • JESD204B data interface to simplify digital interface, compliant up to 5.0Gbps lane rates
  • Supports JESD204B subclass 1 for synchronization and compatibility
  • Channels A and B can be configured separately (...)

Software development

JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
  • Compatible with TSW1400, TSW1405, TSW1406, TSW14J10, TSW14J50, TSW14J56, TSW14J57 and TSW14J58 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SBAM247.ZIP (31 KB) - IBIS Model
SLAM308.ZIP (1371 KB) - IBIS-AMI Model
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

CAD/CAE symbols

Package Pins Download
VQFN (RGC) 64 View options

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