SLASE67A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
D15 | D14 | D13 | D12 | D11 | D10 | D9 | D8 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 | 0 | CLK SW AB | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
D9 | CLK SW AB | R/W | 0 | User should set this bit to 1 when changing the clock phase of the clock divider AB. After the change is complete user needs to write this bit back to 0. |
D8 | R | 1 | Reads back 1 | |
D6 | R | 1 | Reads back 1 | |
D2 | R | 1 | Reads back 1 |