SLASE67A January 2015 – August 2019 ADS54J54
PRODUCTION DATA.
The ADS54J54 is equipped with two internal dividers on the clock input – one on channel AB and one on channel CD. The clock divider allows operation with a faster input clock simplifying the system clock distribution design. The clock dividers can be bypassed (/1) for operation with a 500-MHz clock while /2 option supports a maximum input clock of 1 GHz and the /4 option a maximum input clock frequency of 2 GHz. Different divider options can be selected for channel AB and channel CD clock output. By default the divider output of channel AB block is routed to all 4 channels but the configuration can be customized with different SPI register settings to use either the channel AB or CD divider blocks for any two channels.