SLUSE31A April   2020  – February 2021 BQ25968

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charging System
      2. 9.3.2  Battery Charging Profile
      3. 9.3.3  Control State Diagram for System Implementation
      4. 9.3.4  Device Power Up
      5. 9.3.5  Switched Cap Function
        1. 9.3.5.1 Theory of Operation
      6. 9.3.6  Charging Start-Up
      7. 9.3.7  Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
      8. 9.3.8  Device Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
      9. 9.3.9  INT Pin, STAT, FLAG, and MASK Registers
      10. 9.3.10 CDRVH and CDRVL_ADDRMS Functions
      11. 9.3.11 Parallel Operation Using Master and Slave Modes
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Modes and Protection Status
        1. 9.4.1.1 Input Overvoltage, Overcurrent, Undercurrent and Short-Circuit Protection
        2. 9.4.1.2 Battery Overvoltage and Overcurrent Protection
        3. 9.4.1.3 Cycle-by-Cycle Current Limit
    5. 9.5 Programming
      1. 9.5.1 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1 Customer Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Standalone Application Information (for use with switching charger)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Parallel BQ25968 for Higher Power Applications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

GUID-EA4225E3-FC5B-4E40-8603-A6C3E1789675-low.svgFigure 7-1 YFF Package 56-Pin DSBGABottom View
Table 7-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
A1, B1, C1, D1, E1, F1, G1, H1 GND P Power ground.
A2, B2, C2, D2 CFL2 P Switched cap flying cap connection. Connect three 22-µF capacitors in parallel between this pin and CFH2.
A3, B3, C3, D3, E3, F3, G3, H3 VOUT P Device power output. Connect a 22-µF capacitor between this pin and GND.
A4, B4, C4, D4 CFH2 P Switched cap flying cap connection. Connect a three 22-µF capacitors in parallel between this pin and CFL2. Other capacitor values and number can be used, and will affect VOUT ripple and efficiency.
A5 TSBAT_SYNCOUT AIO Battery temperature voltage input and Master Mode SYNCOUT. Requires external resistor divider, NTC, and voltage reference. See the TSBAT section for choosing the resister divider values. If the device is in Master Mode, connect this pin to SYNCIN of the Slave device.
A6 SRP AI Positive input for low side battery current sensing. Place a 2-mΩ or 5-mΩ RSENSE between SRN and SRP. Short to SRN and SRP together and GND if not used. Since the device senses the current by measuring the voltage drop across RSENSE, if other than 2-mΩ or 5-mΩ RSENSE is used, the host device will have to scale the IBAT_ADC reading appropriately.
A7 BATP_SYNCIN AI Positive input for battery voltage sensing. Connect to positive terminal of battery pack. Place 100-Ω to 1-kΩ series resistance between pin and positive terminal. If configured as a Slave for parallel configuration, this pin functions as SYNCIN, and connect to SYNCOUT of Master, and connect a 1-kΩ pullup resistor to REGN.
B5, C5, D5, E5, F5, G5 PMID P PMID is the input to the switched cap power stage. Connect 10-µF cap to PMID.
B6 SRN AI Negative input for low side battery current sensing. Place a 2-mΩ or 5-mΩ RSENSE between SRN and SRP. Short to SRP and SRN together and to GND if not used.
B7 BATN AI Negative input for batter voltage sensing. Connect to negative terminal of battery pack. Place 100-Ω/1-k series resistance between pin and negative terminal.
C6, D6, E6, F6 VBUS P Device power input. Place a 1-µF bypass cap to GND as close as possible to these pins.
C7 INT DO Open drain, active low interrupt output. Pull up to voltage with 10-kΩ resistor. Normally high, the device asserts low to report status and faults. INT is pulsed low for tINT.
D7 OVPGATE AO External OVP FET N-channel gate drive pin. A minimum of 8-nC of capacitance is required from the OVP FET Gate to Source. Float if not in use.
E2, F2, G2, H2 CFL1 P Switched cap flying cap connection. Connect three 22-µF caps in parallel between this pin an CFH1. Other capacitor values and number can be used, and will affect VOUT ripple and efficiency.
E4, F4, G4, H4 CFH1 P Switched cap flying cap connection. Connect three 22-µF caps in parallel between this pin and CFL1. Other capacitor values and number can be used, and will affect VOUT ripple and efficiency.
E7 VAC AI Device power input. Tie to VBUS if BQ25971 (no external OVP FET).
F7 SCL DIO I2C interface data. Pull up to voltage with 1-kΩ resistor.
G6 REGN AO LDO output. Connect a 4.7-µF cap between this pin and GND.
G7 SDA DI I2C interface clock. Pull up to voltage with 1-kΩ resistor.
H5 TSBUS AI BUS temperature voltage input. Requires external resistor divider, NTC, and voltage reference.
H6 CDRVH AIO Charge pump for gate drive. Connect a 0.22-µF cap between CDRVH and CDRVL.
H7 CDRVL_ADDRMS AIO Charge pump for gate drive. Connect a 0.22-µF cap between CDRVH and CDRVL. During POR, this pin is used to assign the address of the device and the mode of the device as Standalone, Master, or Slave. See Table 9-2 in Section 9.3.10 for a table of functionality.
(1) Type: P = Power , AIO = Analog Input/Output , AI = Analog Input, DO = Digital Output, AO = Analog Output, DIO = Digital Input/Output