SLUSE31A April   2020  – February 2021 BQ25968

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charging System
      2. 9.3.2  Battery Charging Profile
      3. 9.3.3  Control State Diagram for System Implementation
      4. 9.3.4  Device Power Up
      5. 9.3.5  Switched Cap Function
        1. 9.3.5.1 Theory of Operation
      6. 9.3.6  Charging Start-Up
      7. 9.3.7  Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
      8. 9.3.8  Device Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
      9. 9.3.9  INT Pin, STAT, FLAG, and MASK Registers
      10. 9.3.10 CDRVH and CDRVL_ADDRMS Functions
      11. 9.3.11 Parallel Operation Using Master and Slave Modes
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Modes and Protection Status
        1. 9.4.1.1 Input Overvoltage, Overcurrent, Undercurrent and Short-Circuit Protection
        2. 9.4.1.2 Battery Overvoltage and Overcurrent Protection
        3. 9.4.1.3 Cycle-by-Cycle Current Limit
    5. 9.5 Programming
      1. 9.5.1 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1 Customer Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Standalone Application Information (for use with switching charger)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Parallel BQ25968 for Higher Power Applications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.2.1.2 Detailed Design Procedure

The first step is the determine if an external OVP FET is required in the application. Choosing to include the external OVP FET allows protection of the device if an over-voltage event occurs. If not using the external OVP FET capable part (BQ25970 or BQ25968), it is recommended to have some other TVS mechanism to protect the device.

The next step is to determine the number of CFLY caps to put on each phase of the design. It is important to consider the current rating of the caps, their ESR, and the capacitance rating. Be sure to consider the bias voltage derating for the caps, as the CFLY caps are biased to half of the input voltage, and this will affect their effective capacitance. An optimal system will have four 22-µF caps per phase, for a total of 8 caps per device. The recommended parts for this configuration are shown below, and result in the lowest cost, acceptable efficiency, and acceptable voltage and current ripple. It is possible to use fewer caps, with a minimum recommendation of 3. Using fewer caps will result in higher voltage and current ripple on the output, as well as lower efficiency. Using more than 4 caps per phase will not significantly improve the output voltage or current ripple, or efficiency.

The default switching frequency, fSW, for the power stage is 500 kHz. The switching frequency can be adjusted in register 0x0Bh using the FSW_SET bits. Using a lower switching frequency will increase the efficiency, but also increase the voltage and current ripple. If using 3 22-µF caps per phase, it is recommended to use the default fSW of 500 kHz. If using 4 22-µF caps per phase, either 500 kHz or 300 kHz is recommended.

Table 10-1 BQ25968 Capacitors
CAPACITANCE (µF)SIZE, VOLTAGE RATING, TEMP CHARCAPACITOR TYPESUPPLIER(1)COMMENT
200704, 16 V, X5RGRMJN7R61C206ME05MurataLowest ESR (high efficiency) when using four caps
220603, 10 V, X5RGRM188R61A226ME15MurataLowest Cost and Smallest Size (Recommended) when using four caps
(1) See Third-party Products Disclaimer