SLUSE31A April   2020  – February 2021 BQ25968

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Charging System
      2. 9.3.2  Battery Charging Profile
      3. 9.3.3  Control State Diagram for System Implementation
      4. 9.3.4  Device Power Up
      5. 9.3.5  Switched Cap Function
        1. 9.3.5.1 Theory of Operation
      6. 9.3.6  Charging Start-Up
      7. 9.3.7  Integrated 16-Bit ADC for Monitoring and Smart Adapter Feedback
      8. 9.3.8  Device Internal Thermal Shutdown, TSBUS, and TSBAT Temperature Monitoring
      9. 9.3.9  INT Pin, STAT, FLAG, and MASK Registers
      10. 9.3.10 CDRVH and CDRVL_ADDRMS Functions
      11. 9.3.11 Parallel Operation Using Master and Slave Modes
    4. 9.4 Device Functional Modes
      1. 9.4.1 Device Modes and Protection Status
        1. 9.4.1.1 Input Overvoltage, Overcurrent, Undercurrent and Short-Circuit Protection
        2. 9.4.1.2 Battery Overvoltage and Overcurrent Protection
        3. 9.4.1.3 Cycle-by-Cycle Current Limit
    5. 9.5 Programming
      1. 9.5.1 F/S Mode Protocol
    6. 9.6 Register Maps
      1. 9.6.1 Customer Registers
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Standalone Application Information (for use with switching charger)
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Parallel BQ25968 for Higher Power Applications
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.4 Device Power Up

The device is powered from the greater of either VBUS or VOUT (battery). The voltage must be greater than the VBUSPRESENT or VOUTPRESENT threshold to be a valid supply. However, the device will start drawing power once the voltage rises above the VBUSUVLO or VOUTUVLO threshold.

The device has a watchdog timer, which is enabled by default. If the device is not read from or written to before the watchdog expires, the part will stop switching. The first read of the watchdog timer flag will always read ‘1’. During initial power up of the device, upon completion of pin detection for address, an INT pulse will be triggered to show a watchdog timeout. The host should not attempt to read or write before this initial INT signal.

The device will not charge when first powered up, as the default charge state is always not enabled. The ADC is available prior to enabling charge so the system parameters are known to the host before enabling charge. If the VOUT voltage is not greater than 3 V, the charger cannot be enabled. The lowest charge voltage allowed on VOUT is 2.8 V falling.

Although the device will depend on the smart adapter to ramp the charging current, the device implements a soft start through QB that limits the ramp current. If the current through QB is greater than the programmed VBUS_OCP, the FET is disabled. The output voltage ramps as the current is increased.