SLUSBV4C June   2018  – June 2025 BQ40Z80

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Primary (1st Level) Safety Features
      2. 6.3.2  Secondary (2nd Level) Safety Features
      3. 6.3.3  Charge Control Features
      4. 6.3.4  Gas Gauging
      5. 6.3.5  Multifunction Pins
      6. 6.3.6  Configuration
        1. 6.3.6.1 Oscillator Function
        2. 6.3.6.2 System Present Operation
        3. 6.3.6.3 Emergency Shutdown
        4. 6.3.6.4 2-Series, 3-Series, 4-Series, 5-Series, or 6-Series Cell Configuration
        5. 6.3.6.5 Cell Balancing
      7. 6.3.7  Battery Parameter Measurements
        1. 6.3.7.1 Charge and Discharge Counting
      8. 6.3.8  Lifetime Data Logging Features
      9. 6.3.9  Authentication
      10. 6.3.10 Tamper Protection
      11. 6.3.11 LED Display
      12. 6.3.12 IATA Support
      13. 6.3.13 Voltage
      14. 6.3.14 Current
      15. 6.3.15 Temperature
      16. 6.3.16 Communications
        1. 6.3.16.1 SMBus On and Off State
        2. 6.3.16.2 SBS Commands
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information Disclaimer
    2. 7.2 Application Information
    3. 7.3 Typical Applications
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
        1. 7.3.2.1 Using the BQ40Z80EVM with BQSTUDIO
        2. 7.3.2.2 High-Current Path
          1. 7.3.2.2.1 Protection FETs
          2. 7.3.2.2.2 Chemical Fuse
          3. 7.3.2.2.3 Lithium-Ion Cell Connections
          4. 7.3.2.2.4 Sense Resistor
          5. 7.3.2.2.5 ESD Mitigation
        3. 7.3.2.3 Gas Gauge Circuit
          1. 7.3.2.3.1 Coulomb-Counting Interface
          2. 7.3.2.3.2 Power Supply Decoupling and PBI
          3. 7.3.2.3.3 System Present
          4. 7.3.2.3.4 SMBus Communication
          5. 7.3.2.3.5 FUSE Circuitry
        4. 7.3.2.4 Secondary-Current Protection
          1. 7.3.2.4.1 Cell and Battery Inputs
          2. 7.3.2.4.2 External Cell Balancing
          3. 7.3.2.4.3 PACK and FET Control
          4. 7.3.2.4.4 Pre-Discharge Control
          5. 7.3.2.4.5 Temperature Output
          6. 7.3.2.4.6 LEDs
      3. 7.3.3 Application Curve
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
        2. 7.5.1.2 ESD Spark Gap
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.2.2.5 ESD Mitigation

A pair of series 0.1µF ceramic capacitors is placed across the PACK+ and PACK– terminals to mitigate external electrostatic discharges. The two devices in series provide continued operation of the pack if one of the capacitors is shorted.

Optionally, place a transorb such as the SMBJ2A across the terminals to improve ESD immunity.