SLUSBV4C June   2018  – June 2025 BQ40Z80

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Primary (1st Level) Safety Features
      2. 6.3.2  Secondary (2nd Level) Safety Features
      3. 6.3.3  Charge Control Features
      4. 6.3.4  Gas Gauging
      5. 6.3.5  Multifunction Pins
      6. 6.3.6  Configuration
        1. 6.3.6.1 Oscillator Function
        2. 6.3.6.2 System Present Operation
        3. 6.3.6.3 Emergency Shutdown
        4. 6.3.6.4 2-Series, 3-Series, 4-Series, 5-Series, or 6-Series Cell Configuration
        5. 6.3.6.5 Cell Balancing
      7. 6.3.7  Battery Parameter Measurements
        1. 6.3.7.1 Charge and Discharge Counting
      8. 6.3.8  Lifetime Data Logging Features
      9. 6.3.9  Authentication
      10. 6.3.10 Tamper Protection
      11. 6.3.11 LED Display
      12. 6.3.12 IATA Support
      13. 6.3.13 Voltage
      14. 6.3.14 Current
      15. 6.3.15 Temperature
      16. 6.3.16 Communications
        1. 6.3.16.1 SMBus On and Off State
        2. 6.3.16.2 SBS Commands
    4. 6.4 Device Functional Modes
  8. 7 Applications and Implementation
    1. 7.1 Application Information Disclaimer
    2. 7.2 Application Information
    3. 7.3 Typical Applications
      1. 7.3.1 Design Requirements
      2. 7.3.2 Detailed Design Procedure
        1. 7.3.2.1 Using the BQ40Z80EVM with BQSTUDIO
        2. 7.3.2.2 High-Current Path
          1. 7.3.2.2.1 Protection FETs
          2. 7.3.2.2.2 Chemical Fuse
          3. 7.3.2.2.3 Lithium-Ion Cell Connections
          4. 7.3.2.2.4 Sense Resistor
          5. 7.3.2.2.5 ESD Mitigation
        3. 7.3.2.3 Gas Gauge Circuit
          1. 7.3.2.3.1 Coulomb-Counting Interface
          2. 7.3.2.3.2 Power Supply Decoupling and PBI
          3. 7.3.2.3.3 System Present
          4. 7.3.2.3.4 SMBus Communication
          5. 7.3.2.3.5 FUSE Circuitry
        4. 7.3.2.4 Secondary-Current Protection
          1. 7.3.2.4.1 Cell and Battery Inputs
          2. 7.3.2.4.2 External Cell Balancing
          3. 7.3.2.4.3 PACK and FET Control
          4. 7.3.2.4.4 Pre-Discharge Control
          5. 7.3.2.4.5 Temperature Output
          6. 7.3.2.4.6 LEDs
      3. 7.3.3 Application Curve
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 Protector FET Bypass and Pack Terminal Bypass Capacitors
        2. 7.5.1.2 ESD Spark Gap
      2. 7.5.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Typical values stated where TA = 25°C and VCC = 21.6V, Min/Max values stated where TA = –40°C to 85°C and VCC = 2.2V to 32V unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
Supply Currents
INORMAL NORMAL mode CPU not active, CHG on. DSG on, High Frequency Oscillator on, Low Frequency Oscillator on, REG18 on, ADC on, ADC_Filter on, CC_Filter on, CC on, LED/Buttons/GPIOs off, SMBus not active, no Flash write 663 µA
ISLEEP SLEEP mode CPU not active, CHG on, DSG on, High Frequency Oscillator off, Low Frequency Oscillator on, REG18 on, ADC off, ADC_Filter off, CC_Filter off, LED/Buttons/GPIOs off, SMBus not active, no Flash write 96 µA
CPU not active, CHG off. DSG on, High Frequency Oscillator off, Low Frequency Oscillator on, REG18 on, ADC off, ADC_Filter off, CC_Filter off, LED/Buttons/GPIOs off, SMBus not active, no Flash write, BAT = 14.4V 90 µA
ISHUTDOWN SHUTDOWN mode CPU not active, CHG off. DSG off, High Frequency Oscillator off, Low Frequency Oscillator off, REG18 off, ADC off, ADC_Filter off, CC_Filter off, LED/Buttons/GPIOs off, SMBus not active, no Flash write, BAT = 14.4V 1.4 µA
Power Supply Control
VSWITCHOVER– BAT to VCC switchover voltage VBAT < VSWITCHOVER– 1.95 2.1 2.2 V
VSWITCHOVER+ VCC to BAT switchover voltage VBAT > VSWITCHOVER– + VHYS 2.9 3.1 3.25 V
VHYS Switchover voltage hysteresis VSWITCHOVER+ – VSWITCHOVER– 1000 mV
ILKG Input Leakage Current BAT pin, BAT = 0V, VCC = 32V, PACK = 32V 1 µA
PACK pin, BAT = 32V, VCC = 0V, PACK = 0V 1
BAT and PACK terminals, BAT = 0V, VCC = 0V, PACK = 0V, PBI = 32V 1
RPD Internal pulldown resistance PACK 30 40 50 kΩ
AFE Power-On Reset
VREGIT– Negative-going voltage input VREG 1.51 1.55 1.59 V
VHYS Power-on reset hysteresis VREGIT+ – VREGIT– 70 100 130 mV
tRST Power-on reset time 200 300 400 µs
AFE Watchdog Reset and Wake Timer
tWDT AFE watchdog timeout tWDT = 500 372 500 628 ms
tWDT = 1000 744 1000 1256 ms
tWDT = 2000 1488 2000 2512 ms
tWDT = 4000 2976 4000 5024 ms
tWAKE AFE wake timer tWAKE = 250 186 250 314 ms
tWAKE = 500 372 500 628 ms
tWAKE = 1000 744 1000 1256 ms
tWAKE = 2000 1488 2000 2512 ms
tFETOFF FET off delay after reset tFETOFF = 512 409 512 614 ms
Internal 1.8V LDO
VREG Regulator voltage 1.6 1.8 2 V
ΔVO(TEMP) Regulator output over temperature ΔVREG / ΔTA, IREG = 10mA ±0.25%
ΔVO(LINE) Line regulation ΔVREG / ΔVBAT, IBAT = 10mA –0.6% 0.5%
ΔVO(LOAD) Load regulation ΔVREG / ΔIREG, IREG = 0mA to 10mA –1.5% 1.5%
IREG Regulator output current limit VREG = 0.9 × VREG(NOM), VIN > 2.2V 20 mA
ISC Regulator short-circuit current limit VREG = 0 × VREG(NOM) 25 40 55 mA
PSRRREG Power supply rejection ratio ΔVBAT / ΔVREG, IREG = 10mA, VIN > 2.5V, f = 10Hz 40 dB
VSLEW Slew rate enhancement voltage threshold VREG 1.58 1.65 V
Voltage Reference 1
VREF1 Internal reference voltage TA = 25°C, after trim 1.215 1.22 1.225 V
VREF1(DRIFT) Internal reference voltage drift TA = 0°C to 60°C, after trim ±50 PPM/°C
TA = –40°C to 85°C, after trim ±80 PPM/°C
Voltage Reference 2
VREF2 Internal reference voltage TA = 25°C, after trim 1.22 1.225 1.23 V
VREF2(DRIFT) Internal reference voltage drift TA = 0°C to 60°C, after trim ±50 PPM/°C
TA = –40°C to 85°C, after trim ±80 PPM/°C
VC1, VC2, VC3, VC4, VC5, VC6, BAT, PACK
K Scaling factor VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC5–VC4, VC6–VC5 0.198 0.2 0.202 –
VC6–VSS 0.032 0.0333 0.034
BAT–VSS, PACK–VSS 0.0275 0.0286 0.0295
VREF2 0.49 0.5 0.51
VIN Input voltage range VC1–VSS, VC2–VC1, VC3–VC2, VC4–VC3, VC5–VC4, VC6–VC5 –0.2 5 V
VC6–VSS –0.2 30
PACK–VSS –0.2 32
ILKG Input leakage current VC1, VC2, VC3, VC4, VC5, VC6, cell balancing off, cell detach detection off, ADC multiplexer off 1 µA
Cell Balancing and Cell Detach Detection
RCB Internal cell balance resistance RDS(ON) for internal FET switch at 2V < VDS < 4V 200 Ω
ICD Internal cell detach check current VCx > VSS + 0.8V 30 50 70 µA
ADC
VIN Input voltage range Internal reference (VREF1) –0.2 1 V
External reference (VREG) –0.2 0.8 × VREG
Full scale range VFS = VREF1 or VREG –VFS VFS V
INL Integral nonlinearity (1LSB = VREF1/(10 × 2N) = 1.225/(10 × 215) = 37.41µV) 16-bit, best fit, –0.1V to 0.8 × VREF1 ±8.5 LSB
16-bit, best fit, –0.2V to –0.1V ±13.1
OE Offset error 16-bit, post calibration, VFS = VREF1 ±67 ±157 µV
OED Offset error drift 16-bit, post calibration, VFS = VREF1 0.6 3 µV/°C
GE Gain error 16-bit, –0.1V to 0.8 × VFS ±0.2% ±0.8% /FSR
GED Gain error drift 16-bit, –0.1V to 0.8 × VFS 150 PPM/°C
EIR Effective input resistance 8 MΩ
ADC Digital Filter
tCONV Conversion time ADCTL[SPEED1, SPEED0] = 0, 0 31.25 ms
ADCTL[SPEED1, SPEED0] = 0, 1 15.63
ADCTL[SPEED1, SPEED0] = 1, 0 7.81
ADCTL[SPEED1, SPEED0] = 1, 1 1.95
Res Resolution No missing codes, ADCTL[SPEED1, SPEED0] = 0, 0 16 Bits
Eff_Res Effective Resolution With sign, ADCTL[SPEED1, SPEED0] = 0, 0 14 15 Bits
With sign, ADCTL[SPEED1, SPEED0] = 0, 1 13 14
With sign, ADCTL[SPEED1, SPEED0] = 1, 0 11 12
With sign, ADCTL[SPEED1, SPEED0] = 1, 1 9 10
Current Wake Comparator
VWAKE Wake voltage threshold VWAKE = VSRP – VSRN= ± 0.625mV ±0.3 ±0.625 ±0.9 mV
VWAKE = VSRP – VSRN = ± 1.25mV ±0.6 ±1.25 ±1.8
VWAKE = VSRP – VSRN = ± 2.5mV ±1.2 ±2.5 ±3.6
VWAKE = VSRP – VSRN = ± 5mV ±2.4 ±5.0 ±7.2
VWAKE(DRIFT) Temperature drift of VWAKE accuracy 0.5% /°C
tWAKE Time from application of current to wake interrupt 250 700 µs
tWAKE(SU) Wake comparator startup time 500 1000 µs
Coulomb Counter
VINPUT Input voltage range –0.1 0.1 V
VRANGE Full scale range –VREF1 /10 VREF1 /10 V
INL Integral nonlinearity (1LSB = VREF1/(10 × 2N) = 1.215/(10 × 215) = 3.71µV) 16-bit, best fit over input voltage range ±5.2 ±22.3 LSB
OE Offset error 16-bit, post calibration ±5.0 ±10 µV
OED Offset error drift 15-bit + sign, post calibration 0.2 0.3 µV/°C
GE Gain error 15-bit + sign, Over input voltage range ±0.2% ±0.8% /FSR
GED Gain error drift 15-bit + sign, Over input voltage range 150 PPM/°C
EIR Effective input resistance 2.5 MΩ
tCONV Conversion Time Single conversion 250 ms
Eff_Res Effective Resolution Single conversion 15 Bits
Current Protection Thresholds
VOCD OCD detection threshold voltage range VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –16.6 –100 mV
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –8.3 –50 mV
ΔVOCD OCD detection threshold voltage program step VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –5.56 mV
VOCD = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –2.78 mV
VSCC SCC detection threshold voltage range VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 44.4 200 mV
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 22.2 100 mV
ΔVSCC SCC detection threshold voltage program step VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 22.2 mV
VSCC = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 11.1 mV
VSCD1 SCD1 detection threshold voltage range VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –44.4 –200 mV
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –22.2 –100 mV
ΔVSCD1 SCD1 detection threshold voltage program step VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –22.2 mV
VSCD1 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –11.1 mV
VSCD2 SCD2 detection threshold voltage range VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –44.4 –200 mV
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –22.2 –100 mV
ΔVSCD2 SCD2 detection threshold voltage program step VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 1 –22.2 mV
VSCD2 = VSRP – VSRN, PROTECTION_CONTROL[RSNS] = 0 –11.1 mV
VOFFSET OCD, SCC, and SCDx offset error Post-trim –2.5 2.5 mV
VSCALE OCD, SCC, and SCDx scale error No trim –10% 10%
Post-trim –5% 5%
Current Protection Timing
tOCD OCD detection delay time 1 31 ms
ΔtOCD OCD detection delay time program step 2 ms
tSCC SCC detection delay time 0 915 µs
ΔtSCC SCC detection delay time program step 61 µs
tSCD1 SCD1 detection delay time PROTECTION_CONTROL[SCDDx2] = 0 0 915 µs
PROTECTION_CONTROL[SCDDx2] = 1 0 1850 µs
ΔtSCD1 SCD1 detection delay time program step PROTECTION_CONTROL[SCDDx2] = 0 61 µs
PROTECTION_CONTROL[SCDDx2] = 1 121 µs
tSCD2 SCD2 detection delay time PROTECTION_CONTROL[SCDDx2] = 0 0 458 µs
PROTECTION_CONTROL[SCDDx2] = 1 0 915 µs
ΔtSCD2 SCD2 detection delay time program step PROTECTION_CONTROL[SCDDx2] = 0 30.5 µs
PROTECTION_CONTROL[SCDDx2] = 1 61 µs
tDETECT Current fault detect time VSRP – VSRN = VT – 3mV for OCD, SCD1 and SCD2, VSRP – VSRN = VT – 3mV for SCC 160 µs
tACC Current fault delay time accuracy Max delay setting –10% 10%
Internal Temperature Sensor
VTEMPT Internal temperature sensor voltage drift VTEMPP –1.9 –2.1 mV/°C
VTEMPP – VTEMPN, established by design 0.177 0.178 0.179 mV/°C
NTC Thermistor Measurement Support (TS1, TS2, Pins 12 and 13 configured as TS3 and TS4)
RNTC(PU) Internal pullup resistance TS1 14.4 18 21.6 kΩ
TS2 14.4 18 21.6 kΩ
TS3 14.4 18 21.6 kΩ
TS4 14.4 18 21.6 kΩ
RNTC(DRIFT) –360 –280 –200 PPM/°C
Low-Voltage General Purpose I/O (Multifunction Pins 12 and 13 configured as GPIO)
VIH High-level input 0.65 × VREG V
VIL Low-level input 0.35 × VREG V
VOH Output voltage high Output high, pullup enabled, IOH = –1.0mA 0.75 × VREG V
Output high, pullup enabled, IOH = –10µA
VOL Output voltage low Output Low, IOL = 1mA 0.2 × VREG V
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA
High-Voltage General Purpose I/O (multifunction pins 15, 16, 17 configured as GPIO, PRES, DISP, or SHUTDN Pin 15 configured as GPIO; Pin 16 configured as PDSG)
VIH High-level input 1.3 V
VIL Low-level input 0.55 V
VOH Output voltage high Output enabled, VBAT > 5.5V, IOH = –0µA 3.5 V
Output enabled, VBAT > 5.5V, IOH = –10µA 1.8
VOL Output voltage low Output disabled, IOL = 1.5mA 0.4 V
CIN Input capacitance 5 pF
ILKG Input leakage current 3 µA
RO Output reverse resistance Between GPIO, PRES, DISP, SHUTDN, PDSG, and PBI 8 kΩ
General Purpose I/O with Constant Current Sink (Multifunction Pins 20, 21, 22 configured as LEDCNTLx)
VIH High-level input LEDCNTLx 1.45 V
VIL Low-level input LEDCNTLx 0.55 V
VOH Output voltage high LEDCNTLx, Output Enabled, VBAT > 3.0V, IOH = –22.5mA VBAT – 1.6 V
VOL Output voltage low LEDCNTLx, Output Disabled, VBAT > 3.0V, IOH = 3mA 0.4 V
ISC High level output current protection LEDCNTLx –30 –45 –60 mA
IOL Low level output current LEDCNTLx, VBAT > 3.0V, VOL > 0.4V 15.75 22.5 29.25 mA
ILEDCNTLx Current matching between outputs LEDCNTLx, VBAT = VLED + 2.5V +/–1%
CIN Input capacitance LEDCNTLx 20 pF
ILKG Input leakage current LEDCNTLx 1 µA
fLED Frequency of LED pattern LEDCNTLx 124 Hz
tSHUTDOWN Thermal shutdown LEDCNTLx, established by design 120 135 150 °C
General Purpose I/O (Multifunction Pins 20, 21, 22 configured as GPIO) (Pin 20 configured as PDSG)
VIH High-level input 1.45 V
VIL Low-level input 0.55 V
VOH Output voltage high Output enabled, VBAT > 3.0V, IOH = –22.5mA VBAT – 1.6 V
Output disabled, IOL = 3mA 0.4 V
ISC High level output current protection –30 –45 –60 mA
IOL Low level output current VBAT > 3.0V, VOL > 0.4V 15.75 22.5 29.25 mA
CIN Input capacitance 20 pF
ILKG Input leakage current 1 uA
SMBD, SMBC High Voltage I/O
VIH Input voltage high SMBC, SMBD, VREG = 1.8V 1.3 V
VIL Input voltage low SMBC, SMBD, VREG = 1.8V 0.8 V
VOL Output low voltage SMBC, SMBD, VREG = 1.8V, IOL = 1.5mA 0.4 V
CIN Input capacitance 5 pF
ILKG Input leakage current 1 µA
RPD Pulldown resistance 0.7 1 1.3 MΩ
SMBus
fSMB SMBus operating frequency SLAVE mode, SMBC 50% duty cycle 10 100 kHz
fMAS SMBus master clock frequency MASTER mode, no clock low slave extend 51.2 kHz
tBUF Bus free time between start and stop 4.7 µs
tHD(START) Hold time after (repeated) start 4 µs
tSU(START) Repeated start setup time 4.7 µs
tSU(STOP) Stop setup time 4 µs
tHD(DATA) Data hold time 300 ns
tSU(DATA) Data setup time 250 ns
tTIMEOUT Error signal detect time 25 35 ms
tLOW Clock low period 4.7 µs
tHIGH Clock high period 4 50 µs
tR Clock rise time 10% to 90% 1000 ns
tF Clock fall time 90% to 10% 300 ns
tLOW(SEXT) Cumulative clock low slave extend time 25 ms
tLOW(MEXT) Cumulative clock low master extend time 10 ms
SMBus XL
fSMBXL SMBus XL operating frequency SLAVE mode, SMBC 50% duty cycle 40 400 kHz
tBUF Bus free time between start and stop 4.7 µs
tHD(START) Hold time after (repeated) start 4 µs
tSU(START) Repeated start setup time 4.7 µs
tSU(STOP) Stop setup time 4 µs
tTIMEOUT Error signal detect time 5 20 ms
tLOW Clock low period 20 µs
tHIGH Clock high period 20 µs
FUSE Drive (AFEFUSE)
VOH Output voltage high VBAT ≥ 8V, CL = 1nF, IAFEFUSE = 0µA 6 7 8.65 V
VBAT < 8V, CL = 1nF, IAFEFUSE = 0µA VBAT – 0.1 VBAT V
VIH High-level input 1.5 2 2.5 V
IAFEFUSE(PU) Internal pullup current VBAT < 8V, VAFEFUSE = VSS 150 330 nA
RAFEFUSE Output impedance 2 2.6 3.2 kΩ
CIN Input capacitance 5 pF
tDELAY Fuse trim detection delay 128 256 µs
tRISE Fuse output rise time 5 20 µs
N-channel FET Drive (CHG, DSG)
Output voltage ratio RatioDSG = (VDSG – VBAT) / VBAT, 2.2V < VBAT < 4.92V, 10MΩ between PACK and DSG 2.133 2.333 2.45 ––
RatioCHG = (VCHG – VBAT) / VBAT, 2.2V < VBAT < 4.92V, 10MΩ between BAT and CHG 2.133 2.333 2.433 ––
VFETON Output voltage, CHG and DSG on VDSG(ON) = (VDSG – VBAT), VBAT ≥ 4.92V (up to 32V), 10MΩ between PACK and DSG 10.5 11.5 12.5 V
VCHG(ON) = (VCHG – VBAT), VBAT ≥ 4.92V (up to 32V), 10MΩ between BAT and CHG 10.5 11.5 12.5 V
VFETOFF Output voltage, CHG and DSG off VDSG(OFF) = (VDSG – VPACK), 10MΩ between PACK and DSG –0.4 0.4 V
VCHG(OFF) = (VCHG – VBAT), 10MΩ between BAT and CHG –0.4 0.4 V
tR Rise time VDSG from 0% to 35% VDSG(ON)(TYP), VBAT ≥ 2.2V, CL = 4.7nF between DSG and PACK, 5.1kΩ between DSG and CL, 10MΩ between PACK and DSG 200 500 µs
VCHG from 0% to 35% VCHG(ON)(TYP), VBAT ≥ 2.2V, CL = 4.7nF between CHG and BAT, 5.1kΩ between CHG and CL, 10MΩ between BAT and CHG 200 500 µs
tF Fall time VDSG from VDSG(ON)(TYP) to 1V, VBAT ≥ 2.2V, CL = 4.7nF between DSG and PACK, 5.1kΩ between DSG and CL, 10MΩ between PACK and DSG 40 300 µs
VCHG from VCHG(ON)(TYP) to 1V, VBAT ≥ 2.2V, CL = 4.7nF between CHG and BAT, 5.1kΩ between CHG and CL, 10MΩ between BAT and CHG 40 200 µs
P-channel FET Drive (PCHG)
VFETON Output voltage, PCHG on VPCHG(ON) = VCC – VPCHG, 10MΩ between VCC and CHG, VBAT ≥ 8V 6 7 8 V
VFETOFF Output voltage, PCHG off VPCHG(OFF) = VCC – VPCHG, 10MΩ between VCC and CHG –0.4 0.4 V
tR Rise time VPCHG from 10% to 90% VPCHG(ON)(TYP), VSS ≥ 8V, CL = 4.7nF between PCHG and VCC, 5.1kΩ between PCHG and CL, 10MΩ between VCC and CHG 40 200 µs
tF Fall time VPCHG from 90% to 10% VPCHG(ON)(TYP), VSS ≥ 8V, CL = 4.7nF between PCHG and VCC, 5.1kΩ between PCHG and CL, 10MΩ between VCC and CHG 40 200 µs
High-Frequency Oscillator
fHFO Operating frequency 16.78 MHz
fHFO(ERR) Frequency error TA = –20°C to 70°C, includes frequency drift –2.5% ±0.25% 2.5%
TA = –40°C to 85°C, includes frequency drift –3.5% ±0.25% 3.5%
tHFO(SU) Start-up time TA = –20°C to 85°C, CLKCTL[HFRAMP] = 1, oscillator frequency within ±3% of nominal 4 ms
TA = –20°C to 85°C, CLKCTL[HFRAMP] = 0, oscillator frequency within ±3% of nominal 100 µs
Low-Frequency Oscillator
fLFO Operating frequency 262.144 kHz
fLFO(ERR) Frequency error TA = –20°C to 70°C, includes frequency drift –1.5% ±0.25% 1.5%
TA = –40°C to 85°C, includes frequency drift –2.5% ±0.25% 2.5%
tLFO(FAIL) Failure detection frequency 30 80 100 kHz
Instruction Flash
Data retention 10 Years
Flash programming write cycles 1000 Cycles
tPROGWORD Word programming time 40 µs
tMASSERASE Mass-erase time 40 ms
tPAGEERASE Page-erase time 40 ms
tFLASHREAD Flash-read current 2 mA
tFLASHWRITE Flash-write current 5 mA
IFLASHERASE Flash-erase current 15 mA
Data Flash
Data retention 10 Years
Flash programming write cycles 20000 Cycles
tPROGWORD Word programming time 40 µs
tMASSERASE Mass-erase time 40 ms
tPAGEERASE Page-erase time 40 ms
tFLASHREAD Flash-read current 1 mA
tFLASHWRITE Flash-write current 5 mA
IFLASHERASE Flash-erase current 15 mA
ECC Authentication
INORMAL+AUTH NORMAL mode + Authentication CPU active, CHG on. DSG on, High Frequency Oscillator on, Low Frequency Oscillator on, REG18 on, ADC on, ADC_Filter on, CC_Filter on, CC on, SMBus not active, Authentication Start 1350 µA
tSIGN EC-KCDSA signature signing time 3.8V < VCC or BAT < 32V 375 ms
Number of Authentication operations 20000 Operations