SLUSCU0J March   2018  – March 2022 BQ77915

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Design Example

This example shows how to design protection for an 18-V Li-ion battery pack using 4.2-V cells with the following requirements:

  • The system will operate from 15 V to 21.5 V.
  • The battery must allow 4-A continuous current.
  • The battery must protect with 8-A discharge current > 500 ms.
  • The battery must have short circuit protection in < 2 ms.
  • The system is for operation in an office environment: 10°C to 30°C.
  • The cell normal charge voltage is 4.2 ±0.05 V to 0.05 C.
  • The cell cutoff voltage is 2.75 V.
  • The charge temperature is 0°C to 45°C.
  • A cell configuration is selected to provide 5 Ah over the system range of operation.
  • The cell assembly is capable of > 30-A short circuit current.
  • Cell balancing is desired with a current of 10% of termination current.
  • Low current drain is desired when the pack is removed from the system.
  • Load removal for fault recovery is required. Recovery by connecting the charger is acceptable.

To start the design:

  1. Start the schematic:
    • An 18-V pack using 3.6-V nominal cells requires a 5-series configuration. A single BQ77915 device is needed.
    • Follow the 5-series reference schematic in this document. Follow the recommended design parameters in Design Requirements.
    • Because a single device is needed, CTRC and CTRD are connected directly to GND.
    • The power FET used in this type of application usually has an absolute maximum of 20-V Vgs. For an 18-V pack design, transient voltage during an OCD may exceed 20 V, so the diode across the 1-MΩ RCHG2 is used. RCHG helps to slow the charge FET from turning on.
    • Because a charger connection for UV recovery is acceptable, the condition in Section 10.1.1.4 is not a concern. A 1-MΩ RGS_CHG can be used for the schematic.
    • The optional sense input filter is selected for the circuit.
    • Because low current storage is desired, the PRES pin is brought out of the pack for control by the system. The standard recommended RHIB value is used.
    • Because cell balancing is required:
      • Connect the CBI pin to VSS.
      • Determine the resistance for the RIN filter resistors. Since the charge taper current will be 0.05 × 5 A or 250 mA, 10% is 25 mA. With a 4.1-V cell, 25 mA would require 164-Ω resistance. This resistance includes the internal RBAL resistance and two RIN resistors. 75-Ω resistors are selected for RIN.
  2. Decide the value of the sense resistor, RSNS.
    • When selecting the value of RSNS, ensure the voltage drop across SRP and SRN is within the available current protection threshold range.
    • In this example, only one protection threshold is specified. The minimum available OCD threshold is the –10-mV OCD1 threshold, but this would result in an odd value for RSNS and the tolerance of the threshold is 30%. Using the –60-mV threshold of the BQ77915 configuration, a 10-mΩ sense resistor would give a 6-A nominal OCD threshold. With the 20% tolerance, 4 A can pass without OCD and 8 A will always cross the threshold.
    • A 30-A SCD with a 10-mΩ sense resistor would be a nominal 300-mV threshold. Tolerance must be considered and the protection threshold can be lower than the battery capability. The 120-mV threshold of the BQ77915 configuration with a 10-mΩ RSNS will give a 12-A nominal short circuit threshold.
    • Select RSNS = 10 mΩ for this example.
  3. Determine the remaining BQ77915 protection configuration:
    • Charging the cells at a lower than maximum voltage allows a margin on setting the OV threshold. The system could allow a 4.15-V OV, while the cells might allow a 4.3-V OV. Since the charge voltage will be 4.1 V/cell, this is the desired VFC point of the BQ77915 device. The 4200-mV OV threshold and 100 mV VOV – VFC of the BQ77915 device are suitable.
    • OV hysteresis and delay values are not specified requirements. A 1-s delay will be selected. Some hysteresis is desired to prevent cycling if the battery were to reach OV. 200 mV is acceptable.
    • The system will stop operation at a nominal 3 V per cell, while the cells could operate to 2.75 V. Some margin below the 3 V should be allowed, because cell voltages may vary at low states of charge. A 2750-mV threshold option is available, but the existing BQ77915 configuration has the 2900 threshold.
    • UV hysteresis and delay are not specified requirements. A 1-s delay is selected. Generally, a larger UV hysteresis will avoid system cycling from automatic recovery; however, in this design load, removal is required and charger connection is expected for UV recovery. The value could vary, but 400 mV is selected.
    • Open-wire protection is selected at the 100-nA level.
    • tOCD1 or tOCD2 could be programmed to 350 ms to protect in less than 500 ms, or the default BQ77915 180 ms is used. However, the 350 ms can be selected with ROCD. Use 604 kΩ 1% for ROCD.
    • The 2-ms SCD response time allows either SCD delay selection.
    • Overcurrent charge protection is not specified in the requirements. The BQ77915 60-mV setting will allow a 1C charge.
    • For temperature protections, the 0°C to 45°C charge temperature thresholds match the range for the cells. Use the lower range for discharge.
    • The VCBTH – VCBTHL determines the voltage spread during constant current charge when balancing will be allowed. 100 mV allows some spread without balancing.
    • See the summary in Table 10-2.
  4. Review the available release in the Device Comparison Table to determine if it is a suitable option. In this example, the BQ7791500 configuration is suitable. If it is not suitable for your design, contact a TI representative for further assistance and for information on BQ77915 PRODUCT PREVIEW devices.

Table 10-2 Design Example Configuration
ProtectionThresholdHysteresisDelayRecovery Method
OV4.2 V200 mV1 s (default setting)Hysteresis
UV2.9 V400 mV1 s (default setting)Hysteresis + load removal
OW100 nA
(default setting)
(VCx – VCx–1) > 600 mV (typical)
OCD160 mV180 msLoad removal only
OCD260 mV180 ms (350 ms using ROCD)Load removal only
SCD120 mV960 µsLoad removal only
OCC60 mV-—Fixed at 10 msLoad detection only
OTC45°C10°C4.5 sHysteresis
OTD65°C10°C4.5 sHysteresis
UTC0°C10°C4.5 sHysteresis
UTD–10°C10°C4.5 sHysteresis
VOV – VFC100 mV
VCBTH – VCBTL100 mV
VSTART3.8 V