SLUSCU0I March   2018  – September 2020 BQ77915

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
    1.     Pin Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Table
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Device Functionality Summary
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Protection Summary
      2. 9.3.2  Fault Operation
        1. 9.3.2.1  Operation in OV
        2. 9.3.2.2  Operation in UV
        3. 9.3.2.3  Operation in OW
        4. 9.3.2.4  Operation in OCD1
        5. 9.3.2.5  Operation in OCD2
        6. 9.3.2.6  Programming the OCD1/2 Delay Using the OCDP Pin
        7. 9.3.2.7  Operation in SCD
        8. 9.3.2.8  Operation in OCC
        9. 9.3.2.9  Overcurrent Recovery Timer
        10. 9.3.2.10 Load Detection and Load Removal Detection
        11. 9.3.2.11 Operation in OTC
        12. 9.3.2.12 Operation in OTD
        13. 9.3.2.13 Operation in UTC
        14. 9.3.2.14 Operation in UTD
      3. 9.3.3  Protection Response and Recovery Summary
      4. 9.3.4  Cell Balancing
      5. 9.3.5  HIBERNATE Mode Operation
      6. 9.3.6  Configuration CRC Check and Comparator Built-In-Self-Test
      7. 9.3.7  Fault Detection Method
        1. 9.3.7.1 Filtered Fault Detection
      8. 9.3.8  State Comparator
      9. 9.3.9  DSG FET Driver Operation
      10. 9.3.10 CHG FET Driver Operation
      11. 9.3.11 External Override of CHG and DSG Drivers
      12. 9.3.12 Configuring 3-Series, 4-Series, or 5-Series Modes
      13. 9.3.13 Stacking Implementations
      14. 9.3.14 Zero-Volt Battery Charging Inhibition
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power Modes
        1. 9.4.1.1 Power On Reset (POR)
        2. 9.4.1.2 NORMAL Mode
        3. 9.4.1.3 FAULT Mode
        4. 9.4.1.4 HIBERNATE Mode
        5. 9.4.1.5 SHUTDOWN Mode
        6. 9.4.1.6 Customer Fast Production Test Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Recommended System Implementation
        1. 10.1.1.1 CHG and DSG FET Rise and Fall Time
        2. 10.1.1.2 Protecting CHG and LD
        3. 10.1.1.3 Protecting the CHG FET
        4. 10.1.1.4 Using Load Detect for UV Fault Recovery
        5. 10.1.1.5 Temperature Protection
        6. 10.1.1.6 Adding RC Filters to the Sense Resistor
        7. 10.1.1.7 Using the State Comparator in an Application
          1. 10.1.1.7.1 Examples
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Design Example
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Cell Balancing

Cell balancing is performed by comparing the cell voltages with respect to cell balancing threshold voltages, evaluating the results of the comparison and controlling the cell balancing FET, which over a period of time will allow for closer cell voltages, thereby extending battery pack life. The conditions for performing cell balancing are: CBI is connected to VSS, no device in the stack is in a fault condition, and the pack is charging. The State Comparator section lists the conditions for the device's charging state.

CBI is the cell balancing input pin. It enables cell balancing function for the device.

  • Leave the CBI pin floating to disable cell balancing. An internal circuit pulls up the CBI pin to AVDD in this case.
  • Connect CBI to VSS to enable cell balancing.

In a single device, cell balancing of all the odd numbered cells can happen at the same time, and balancing of all the even numbered cells can also happen at the same time, but odd and even cells are not balanced at the same time. When devices are stacked on top of each other, it must be ensured in the PCB layout that the trace from VC5 pin to a cell and the trace from the VC0 pin of the next upper device to the immediately higher cell are kept separate.

All cell balancing FETs are turned off during voltage measurements. If odd numbered and even numbered cells need balancing at the same time, one single cycle time tBAL is dedicated for odd numbered cells alone followed by the next tBAL dedicated for even numbered cells alone. See an example of adjacent cell balancing in Figure 9-1.

GUID-8810151E-40E1-4945-B5A8-C64A20CBC6FF-low.pngFigure 9-1 Balancing cells 1, 2, and 3

In a stacked configuration, the CBO pin of the bottom device should be connected to the CBI pin of the next upper device through a 10-kΩ resistor and so forth.

When a cell is in OV, its corresponding balancing FET will be turned on if CBI is connected to VSS and if there are no discharge faults anywhere in the stack. The balancing FET will be ON until the cell voltage drops to VFC or VOV – VHYS_OV, whichever occurs earlier.

GUID-7E3FE3AB-1C04-42D0-AFB6-BE4E2CD4F7A4-low.gifFigure 9-2 Cell-Balancing Algorithm

VCBTL is the lower cell balancing threshold and VCBTH is the upper cell balancing threshold. In Figure 9-2, the balancing FET will be turned on only for the cell CV5. The BQ77915 VSTART is set at 3.8 V; therefore, cell balancing starts only when individual cell voltages exceed 3.8 V. The difference between VCBTH and VCBTL can be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV. The difference between the VOV and VFC can also be programmed in the EEPROM to be between 50 mV and 200 mV, in steps of 50 mV.

When using the integrated MOSFETs for cell balancing, the cell monitor filter resistance RINI controls the amount of cell balancing current the device can supply to the cells. Internal cell balancing should be used for cell balancing currents up to 50 mA. External MOSFETs have to be used if higher cell balancing currents are required. In the case of external balancing, the balancing current is controlled by the resistor RCB in series with the external MOSFET, as shown in Figure 9-3. The pin filter resistance RINE should be 1 kΩ and the capacitance CINE should be 0.1 µF. The gate bias voltage necessary to turn on the FET connected to Cell(n) is generated by the resistor RINE connected to the VC(n–1) pin. The external MOSFET must be selected with a threshold voltage less than 1.7 V.

GUID-02707D67-94BE-466B-870E-D22282C63D3D-low.gifFigure 9-3 Cell Balancing with External MOSFETs