DLPS282 July   2025 DLP473TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
      1.      17
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.1 Absolute Maximum Ratings

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, which may affect device reliability, functionality, and performance, and shorten the device's lifetime.
MINMAXUNIT
SUPPLY VOLTAGE
VDDSupply voltage for LVCMOS core logic and LPSDR low-speed interface (LSIF)(1)–0.52.3V
VDDI Supply voltage for SubLVDS receivers(1)–0.52.3V
VOFFSETSupply voltage for HVCMOS and micromirror electrode(1)(2)–0.511V
VBIASSupply voltage for micromirror electrode(1)–0.519V
VRESETSupply voltage for micromirror electrode(1)–150.5V
| VDDI – VDD |Supply voltage delta (absolute value)(3)0.3V
| VBIAS – VOFFSET |Supply voltage delta (absolute value)(4)11V
| VBIAS – VRESET |Supply voltage delta (absolute value)(5)34V
INPUT VOLTAGE
Input voltage for other inputs – LSIF and LVCMOS(1)–0.5VDD+0.5V
Input voltage for other inputs – SubLVDS(1)(6)–0.5VDDI+0.5V
SUBLVDS INTERFACE (HSIF)
| VID |SubLVDS differential input voltage (absolute value)(6)810mV
| IID |SubLVDS input differential current(6)10mA
CLOCK FREQUENCY
fCLOCKLSIF clock frequency (LS_CLK)100130MHz
TEMPERATURE DIODE
ITEMP_DIODEMax current source into temperature diode120µA
ENVIRONMENTAL
TARRAYTemperature, operating(7)090°C
Temperature, non-operating(7)–4090°C
TDPDew point temperature, operating and non–operating (noncondensing)81°C
(1) All voltage values are concerning the ground terminals (VSS). The following required power supplies must be connected for proper DMD operation: VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.
(2) VOFFSET supply transients must fall within specified voltages.
(3) Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.
(4) Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current draw.
(5) Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current draw.
(6) This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. SubLVDS differential inputs must not exceed the specified limit or damage may result to the internal termination resistors.
(7) The array temperature cannot be measured directly and must be computed analytically from the temperature measured at test point 1 (TP1), as shown in Figure 6-1 and Section 6.6.