DLPS282 July   2025 DLP473TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
      1.      17
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

DLP473TE FXL Package173-Pin PGABottom View Figure 4-1 FXL Package173-Pin PGABottom View
CAUTION:

Properly manage the layout and the operation of signals identified in the Pin Functions table to make sure there is reliable, long-term operation of the 0.47” 4K UHD S460 DMD. Refer to the PCB Design Requirements for TI DLP Digital Micromirror Devices application report for specific details and guidelines before designing the board.
Table 4-1 Pin Functions
PIN INPUT-OUTPUT(1) DESCRIPTION TERMINATION TRACE LENGTH (mm)
NAME ID
D_AP(0) R2 I High-speed Differential Data Pair lane A0 Differential 100Ω 8.204
D_AN(0) P2 I High-speed Differential Data Pair lane A0 Differential 100Ω 8.201
D_AP(1) T4 I High-speed Differential Data Pair lane A1 Differential 100Ω 9.95
D_AN(1) T3 I High-speed Differential Data Pair lane A1 Differential 100Ω 9.95
D_AP(2) P1 I High-speed Differential Data Pair lane A2 Differential 100Ω 8.439
D_AN(2) N1 I High-speed Differential Data Pair lane A2 Differential 100Ω 8.44
D_AP(3) R5 I High-speed Differential Data Pair lane A3 Differential 100Ω 10.166
D_AN(3) R6 I High-speed Differential Data Pair lane A3 Differential 100Ω 10.167
D_AP(4) T5 I High-speed Differential Data Pair lane A4 Differential 100Ω 12.672
D_AN(4) T6 I High-speed Differential Data Pair lane A4 Differential 100Ω 12.673
D_AP(5) K2 I High-speed Differential Data Pair lane A5 Differential 100Ω 5.097
D_AN(5) L2 I High-speed Differential Data Pair lane A5 Differential 100Ω 5.094
D_AP(6) T7 I High-speed Differential Data Pair lane A6 Differential 100Ω 13.416
D_AN(6) T8 I High-speed Differential Data Pair lane A6 Differential 100Ω 13.416
D_AP(7) J1 I High-speed Differential Data Pair lane A7 Differential 100Ω 6.356
D_AN(7) K1 I High-speed Differential Data Pair lane A7 Differential 100Ω 6.356
DCLK_AP L1 I High-speed Differential Clock A Differential 100Ω 7.247
DCLK_AN M1 I High-speed Differential Clock A Differential 100Ω 7.247
D_BP(0) T13 I High-speed Differential Data Pair lane B0 Differential 100Ω 9.167
D_BN(0) T14 I High-speed Differential Data Pair lane B0 Differential 100Ω 9.168
D_BP(1) T17 I High-speed Differential Data Pair lane B1 Differential 100Ω 10.163
D_BN(1) T18 I High-speed Differential Data Pair lane B1 Differential 100Ω 10.163
D_BP(2) T12 I High-speed Differential Data Pair lane B2 Differential 100Ω 12.753
D_BN(2) T11 I High-speed Differential Data Pair lane B2 Differential 100Ω 12.756
D_BP(3) T15 I High-speed Differential Data Pair lane B3 Differential 100Ω 14.679
D_BN(3) T16 I High-speed Differential Data Pair lane B3 Differential 100Ω 14.684
D_BP(4) P20 I High-speed Differential Data Pair lane B4 Differential 100Ω 10.903
D_BN(4) N20 I High-speed Differential Data Pair lane B4 Differential 100Ω 10.901
D_BP(5) M20 I High-speed Differential Data Pair lane B5 Differential 100Ω 10.043
D_BN(5) L20 I High-speed Differential Data Pair lane B5 Differential 100Ω 10.042
D_BP(6) L19 I High-speed Differential Data Pair lane B6 Differential 100Ω 8.167
D_BN(6) K19 I High-speed Differential Data Pair lane B6 Differential 100Ω 8.167
D_BP(7) K20 I High-speed Differential Data Pair lane B7 Differential 100Ω 7.373
D_BN(7) J20 I High-speed Differential Data Pair lane B7 Differential 100Ω 7.373
DCLK_BP R19 I High-speed Differential Clock B Differential 100Ω 10.517
DCLK_BN P19 I High-speed Differential Clock B Differential 100Ω 10.516
D_CP(0) H1 I High-speed Differential Data Pair lane C0 Differential 100Ω 6.308
D_CN(0) G1 I High-speed Differential Data Pair lane C0 Differential 100Ω 6.308
D_CP(1) H2 I High-speed Differential Data Pair lane C1 Differential 100Ω 4.941
D_CN(1) G2 I High-speed Differential Data Pair lane C1 Differential 100Ω 4.939
D_CP(2) F1 I High-speed Differential Data Pair lane C2 Differential 100Ω 7.011
D_CN(2) E1 I High-speed Differential Data Pair lane C2 Differential 100Ω 7.009
D_CP(3) E2 I High-speed Differential Data Pair lane C3 Differential 100Ω 6.959
D_CN(3) D2 I High-speed Differential Data Pair lane C3 Differential 100Ω 6.959
D_CP(4) A4 I High-speed Differential Data Pair lane C4 Differential 100Ω 10.185
D_CN(4) A5 I High-speed Differential Data Pair lane C4 Differential 100Ω 10.185
D_CP(5) A7 I High-speed Differential Data Pair lane C5 Differential 100Ω 9.34
D_CN(5) A6 I High-speed Differential Data Pair lane C5 Differential 100Ω 9.34
D_CP(6) B7 I High-speed Differential Data Pair lane C6 Differential 100Ω 9.109
D_CN(6) B8 I High-speed Differential Data Pair lane C6 Differential 100Ω 9.11
D_CP(7) B5 I High-speed Differential Data Pair lane C7 Differential 100Ω 7.548
D_CN(7) B4 I High-speed Differential Data Pair lane C7 Differential 100Ω 7.551
DCLK_CP A9 I High-speed Differential Clock C Differential 100Ω 11.431
DCLK_CN A8 I High-speed Differential Clock C Differential 100Ω 11.429
D_DP(0) H19 I High-speed Differential Data Pair lane D0 Differential 100Ω 5.531
D_DN(0) G19 I High-speed Differential Data Pair lane D0 Differential 100Ω 5.53
D_DP(1) H20 I High-speed Differential Data Pair lane D1 Differential 100Ω 7.153
D_DN(1) G20 I High-speed Differential Data Pair lane D1 Differential 100Ω 7.152
D_DP(2) F20 I High-speed Differential Data Pair lane D2 Differential 100Ω 7.449
D_DN(2) E20 I High-speed Differential Data Pair lane D2 Differential 100Ω 7.449
D_DP(3) E19 I High-speed Differential Data Pair lane D3 Differential 100Ω 7.592
D_DN(3) D19 I High-speed Differential Data Pair lane D3 Differential 100Ω 7.592
D_DP(4) B19 I High-speed Differential Data Pair lane D4 Differential 100Ω 9.968
D_DN(4) B18 I High-speed Differential Data Pair lane D4 Differential 100Ω 9.967
D_DP(5) A18 I High-speed Differential Data Pair lane D5 Differential 100Ω 10.435
D_DN(5) A17 I High-speed Differential Data Pair lane D5 Differential 100Ω 10.435
D_DP(6) B16 I High-speed Differential Data Pair lane D6 Differential 100Ω 9.291
D_DN(6) B15 I High-speed Differential Data Pair lane D6 Differential 100Ω 9.293
D_DP(7) A16 I High-speed Differential Data Pair lane D7 Differential 100Ω 9.269
D_DN(7) A15 I High-speed Differential Data Pair lane D7 Differential 100Ω 9.274
DCLK_DP D20 I High-speed Differential Clock D Differential 100Ω 9.019
DCLK_DN C20 I High-speed Differential Clock D Differential 100Ω 9.02
LS_WDATA L3 I Low speed interface (LSIF) write data 3.907
LS_CLK P4 I Low speed interface (LSIF) clock 4.52
LS_RDATA_A N4 O LPSDR Output 2.812
LS_RDATA_B M3 O LPSDR Output 2.925
LS_RDATA_C J4 O LPSDR Output 3.54
LS_RDATA_D K3 O LPSDR Output 3.094
DMD_DEN_ARSTZ H4 I ARSTZ 5.06
TP0 D18 I 4.175
TP1 C17 I 4.334
TP2 C18 I 0.34971
TEMP_N E17 I Temp Diode N 2.676
TEMP_P F17 I Temp Diode P 2.146
VDD A10, A12, A13, A20, B2, B10, B11, B14, C4, D1, D4, E3, E18, F3, F4, G17, J3, J18, M18, N3, N18, R3, R8, R10, R12, R13, R18, T9 P Digital Core Supply Voltage
VDDI D3, F18, G4, H18, K4, K18, L18, M4 P
VRESET T2, T19 P
VBIAS R1, R20 P
VOFFSET D17, E4, T1, T20 P
VSS A3, A11, A14, A19, B3, B6, B9, B12, B13, B17, B20, C1, C2, C3, C19, F2, F19, G3, G18, H3, J2, J19, L4, M2, M19, N2, N19, P3, P18, R4, R7, R9, R11, R14, R17, T10 G Ground
N/C H17, R16, R15, P17, N17, M17, L17, K17, J17, NC No Connect Pin None
(1) I=Input, O=Output, P=Power, G=Ground, NC = No Connect