DLPS282 July   2025 DLP473TE

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5.     11
    6.     12
    7. 5.5  Thermal Information
    8. 5.6  Electrical Characteristics
    9. 5.7  Switching Characteristics
    10. 5.8  Timing Requirements
      1.      17
    11. 5.9  System Mounting Interface Loads
    12. 5.10 Micromirror Array Physical Characteristics
    13. 5.11 Micromirror Array Optical Characteristics
    14. 5.12 Window Characteristics
    15. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Window Aperture Illumination Overfill Calculation
    9. 6.9 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.9.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.9.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.9.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.9.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Temperature Sensor Diode
  9. 8 Power Supply Recommendations
    1. 8.1 DMD Power Supply Power-Up Procedure
    2. 8.2 DMD Power Supply Power-Down Procedure
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Device Support
      1. 9.2.1 Device Nomenclature
      2. 9.2.2 Device Markings
    3. 9.3 Documentation Support
      1. 9.3.1 Related Documentation
    4. 9.4 Receiving Notification of Documentation Updates
    5. 9.5 Support Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER(7) TEST CONDITIONS(2) MIN TYP MAX UNIT
CURRENT
IDD Supply current: VDD(3)(4) Typical 70 mA
IDDI Supply current: VDDI(3)(4) Typical 28 mA
IOFFSET Supply current: VOFFSET(5)(6) Typical 7 mA
IBIAS Supply current: VBIAS(5)(6) Typical 1.5 mA
IRESET Supply current: VRESET (6) Typical 3 mA
POWER
PDD Supply power dissipation: VDD(3)(4) Typical 126 mW
PDDI Supply power dissipation: VDDI(3)(4) Typical 51 mW
POFFSET Supply power dissipation: VOFFSET(5)(6) Typical 70 mW
PBIAS Supply power dissipation: VBIAS(5)(6) Typical 27 mW
PRESET Supply power dissipation: VRESET(6) Typical 42 mW
PTOTAL Supply power dissipation Total Typical 316 mW
LPSDR INPUT
VIH High-level input voltage(8)(9)  0.7 × VDD VDD + 0.3 x VDD
VIL Low-level input voltage(8)(9) –0.3 0.3 x VDD x VDD
VIH(AC) AC input high voltage(8)(9) 0.8 × VDD VDD + 0.3 x VDD
VIL(AC) AC input low voltage(8)(9) –0.3 0.2 × VDD x VDD
VHyst Input Hysteresis ( VT+ – VT– ) 0.1 × VDD 0.4 × VDD V
IIL Low level input current VDD = 1.95V, VI = 0V –100 nA
IIH High level input current VDD = 1.95V, VI = 1.95V 135 uA
LPSDR OUTPUT
VOH DC output high voltage(10) IOH = –2mA 0.8 × VDD X VDD
VOL DC output low voltage(10) IOL = 2mA 0.2 × VDD X VDD
CAPACTIANCE
CIN Input capacitance LVCMOS F = 1MHz 10 pF
CIN Input capacitance SubLVDS F = 1MHz 20 pF
COUT Output capacitance F = 1MHz 10 pF
(1) Device electrical characteristics are over Section 5.4 unless otherwise noted.
(2) All voltage values are with respect to the ground pins (VSS).
(3) To prevent excess current, the supply voltage delta | VDDI – VDD | must be less than the specified limit.
(4) Supply power dissipation based on non-compressed commands and data.
(5) To prevent excess current, the supply voltage delta | VBIAS – VOFFSET | must be less than the specified limit.
(6) Supply power dissipation based on three global resets in 200µs.
(7) All power supply connections are required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
(8) LPSDR specifications are for pins LS_CLK and LS_WDATA.
(9) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low-Power Double Data Rate (LPDDR) JESD209B.
(10) LPSDR output specification is for pins LS_RDATA_A, LS_RDATA_B, LS_RDATA_C, LS_RDATA_D.