SLDS274A September   2024  – March 2025 DRV81242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active Mode
          5. 7.3.2.1.5 Limp Home Mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Reverse Current Behavior
        5. 7.3.3.5 Switching Channels in parallel
        6. 7.3.3.6 Bulb Inrush Mode (BIM)
        7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home Mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
        9. 7.3.4.9 Open Load Detection in ON State
          1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
          2. 7.3.4.9.2 Open Load at ON - diagnosis loop
          3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Bulb Inrush Mode Register
          4. 7.3.5.4.4  Input 0 Mapping Register
          5. 7.3.5.4.5  Input 1 Mapping Register
          6. 7.3.5.4.6  Input Status Monitor Register
          7. 7.3.5.4.7  Open Load Current Control Register
          8. 7.3.5.4.8  Output Status Monitor Register
          9. 7.3.5.4.9  Open Load at ON Register
          10. 7.3.5.4.10 EN_OLON Register
          11. 7.3.5.4.11 Configuration Register
          12. 7.3.5.4.12 Output Clear Latch Register
          13. 7.3.5.4.13 FPWM Register
          14. 7.3.5.4.14 PWM0 Configuration Register
          15. 7.3.5.4.15 PWM1 Configuration Register
          16. 7.3.5.4.16 PWM_OUT Register
          17. 7.3.5.4.17 MAP_PWM Register
          18. 7.3.5.4.18 Configuration 2 Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
      2. 8.1.2 Application Plots
    2. 8.2 Typical Application
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Package Footprint Compatibility
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.3.7 Integrated PWM Generator

The device has two independent integrated PWM generators. Each PWM generator can be assigned to one or more channels, and can be programmed with a different duty cycle and frequency.

Both PWM generators refer to a base frequency fINT generated by an internal oscillator. This base frequency can be adjusted using FPWM bits as described below.

Table 7-6 FPWM Settings

FPWM Bits

Delta to fINT

0000b

Reserved

0001b

-37.2%

0010b

-31.9%

0011b

-26.9%

0100b

-21%

0101b

-15.5%

0110b

-10.9%

0111b

-5.8%

1000b

-

1001b

+4.3%

1010b

+8.9%

1011b

+14%

1100b

+19.5%

1101b

+25.6%

1110b

+32.4%

1111b

+40%

For each PWM generator, four parameters can be set:

  • Duty cycle (bits DC0 for PWM Generator 0)
    • 8 bits are available to achieve 0.39% duty cycle resolution
    • When the micro-controller programs a new duty cycle, the PWM generator waits until the previous cycle is completed before using the new duty cycle (this happens also when the duty cycle is either 0% or100% - the new duty cycle is taken with the next PWM cycle)
    • The maximum duty cycle achievable is 99.61% (DC0 set to 11111111b). Achieving 100% is possible by setting FREQ0 to 11b.
  • Frequency (bits FREQ0, FREQ1, FCTR0 and FCTR1 select the divider for fINT to achieve the needed duty cycle)
Table 7-7 PWM Frequency Selection for PWM Generator 0

FCTR0

FREQ0

PWM Frequency

0b

00b

fINT/1024 (corresponding to 100Hz)

0b

01b

 fINT/512 (corresponding to 200Hz)

0b

10b

 fINT/256 (corresponding to 400Hz)

1b

00b

 fINT/128 (corresponding to 800Hz)

1b

01b

 fINT/64 (corresponding to 1600Hz)

1b

10b

 fINT/51.2 (corresponding to 2000Hz)
Table 7-8 PWM Frequency Selection for PWM Generator 1
FCTR1 FREQ1 PWM Frequency
0b 00b fINT/1024 (corresponding to 100Hz)
0b 01b fINT/512 (corresponding to 200Hz)
0b 10b fINT/256 (corresponding to 400Hz)
1b 00b fINT/128 (corresponding to 800Hz)
1b 01b fINT/64 (corresponding to 1600Hz)
1b 10b fINT/51.2 (corresponding to 2000Hz)
  • Channel output control and mapping registers PWM_OUT and MAP_PWM
    • Any channel can be mapped to each PWM Generator
    • Together with 2 parallel input having 4 independent PWM groups of channels with low effort from the point of view of micro-controller resources and SPI data traffic is possible.

Figure 7-12 expands the concept shown in adding the PWM Generators.

DRV81242-Q1 PWM Generator Mapping Figure 7-12 PWM Generator Mapping