SLDS274A September   2024  – March 2025 DRV81242-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Pins
        1. 7.3.1.1 Input Pins
        2. 7.3.1.2 nSLEEP Pin
      2. 7.3.2 Power Supply
        1. 7.3.2.1 Modes of Operation
          1. 7.3.2.1.1 Power-up
          2. 7.3.2.1.2 Sleep mode
          3. 7.3.2.1.3 Idle mode
          4. 7.3.2.1.4 Active Mode
          5. 7.3.2.1.5 Limp Home Mode
        2. 7.3.2.2 Reset condition
      3. 7.3.3 Power Stage
        1. 7.3.3.1 Switching Resistive Loads
        2. 7.3.3.2 Inductive Output Clamp
        3. 7.3.3.3 Maximum Load Inductance
        4. 7.3.3.4 Reverse Current Behavior
        5. 7.3.3.5 Switching Channels in parallel
        6. 7.3.3.6 Bulb Inrush Mode (BIM)
        7. 7.3.3.7 Integrated PWM Generator
      4. 7.3.4 Protection and Diagnostics
        1. 7.3.4.1 Undervoltage on VM
        2. 7.3.4.2 Overcurrent Protection
        3. 7.3.4.3 Over Temperature Protection
        4. 7.3.4.4 Over Temperature Warning
        5. 7.3.4.5 Over Temperature and Overcurrent Protection in Limp Home Mode
        6. 7.3.4.6 Reverse Polarity Protection
        7. 7.3.4.7 Over Voltage Protection
        8. 7.3.4.8 Output Status Monitor
        9. 7.3.4.9 Open Load Detection in ON State
          1. 7.3.4.9.1 Open Load at ON - direct channel diagnosis
          2. 7.3.4.9.2 Open Load at ON - diagnosis loop
          3. 7.3.4.9.3 OLON bit
      5. 7.3.5 SPI Communication
        1. 7.3.5.1 SPI Signal Description
          1. 7.3.5.1.1 Chip Select (nSCS)
            1. 7.3.5.1.1.1 Logic high to logic low Transition
            2. 7.3.5.1.1.2 Logic low to logic high Transition
          2. 7.3.5.1.2 Serial Clock (SCLK)
          3. 7.3.5.1.3 Serial Input (SDI)
          4. 7.3.5.1.4 Serial Output (SDO)
        2. 7.3.5.2 Daisy Chain Capability
        3. 7.3.5.3 SPI Protocol
        4. 7.3.5.4 SPI Registers
          1. 7.3.5.4.1  Standard Diagnosis Register
          2. 7.3.5.4.2  Output control register
          3. 7.3.5.4.3  Bulb Inrush Mode Register
          4. 7.3.5.4.4  Input 0 Mapping Register
          5. 7.3.5.4.5  Input 1 Mapping Register
          6. 7.3.5.4.6  Input Status Monitor Register
          7. 7.3.5.4.7  Open Load Current Control Register
          8. 7.3.5.4.8  Output Status Monitor Register
          9. 7.3.5.4.9  Open Load at ON Register
          10. 7.3.5.4.10 EN_OLON Register
          11. 7.3.5.4.11 Configuration Register
          12. 7.3.5.4.12 Output Clear Latch Register
          13. 7.3.5.4.13 FPWM Register
          14. 7.3.5.4.14 PWM0 Configuration Register
          15. 7.3.5.4.15 PWM1 Configuration Register
          16. 7.3.5.4.16 PWM_OUT Register
          17. 7.3.5.4.17 MAP_PWM Register
          18. 7.3.5.4.18 Configuration 2 Register
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Suggested External Components
      2. 8.1.2 Application Plots
    2. 8.2 Typical Application
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
      2. 8.3.2 Package Footprint Compatibility
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.5.3 SPI Protocol

The relationship between SDI and SDO content during SPI communication is shown in Figure 7-27. SDI line represents the frame sent from the microcontroller and SDO line is the answer provided by the device.

DRV81242-Q1 Relationship Between SDI and SDO During SPI Communication Figure 7-27 Relationship Between SDI and SDO During SPI Communication

The SPI protocol provides the answer to a command frame only with the next transmission triggered by the microcontroller. Although the biggest majority of commands and frames implemented in the device can be decoded without the knowledge of what happened before, considering what the microcontroller sent in the previous transmission to decode the response frame completely is advisable. The sequence of commands to read and write the content of a register looks as follows:

DRV81242-Q1 Register content sent back to microcontroller Figure 7-28 Register content sent back to microcontroller

There are 3 special situations where the frame sent back to the microcontroller is not related directly to the previous received frame:

  • In case an error in transmission happened during the previous frame (for instance, the clock pulses were not multiple of 8 with a minimum of 16 bits), shown below.
  • When the logic supply comes out of Power-On reset condition or after a Software Reset, as shown below.
  • In case of command syntax errors
    • write command starting with 11b instead of 10b
    • read command starting with 00b instead of 01b
    • read or write commands on registers which are reserved or not used
DRV81242-Q1 Response After a Error in Transmission Figure 7-29 Response After a Error in Transmission
DRV81242-Q1 Response After Coming Out Of Power-On Reset at VDD Figure 7-30 Response After Coming Out Of Power-On Reset at VDD
DRV81242-Q1 Response After a Command Syntax Error Figure 7-31 Response After a Command Syntax Error

A summary of all possible SPI commands is presented below, including the answer that the device sends back at the next transmission.

Table 7-9 SPI Command summary

Requested Operation

Frame sent to SDI pin

Frame received from SDO pin with the next command
Read Standard Diagnosis 0xxxxxxxxxxxxx01b (xxxxxxxxxxxxb = don

't care)

 0dddddddddddddddb (Standard Diagnosis)
Write 10 bit register 10pppprrrrrrrrrrb where: ppppb = register address ADDR0, rrrrrrrrrrb = new register content 0dddddddddddddddb (Standard Diagnosis)
Read 10 bit registers 01ppppxxxxxxxx10b where: ppppb = register address ADDR0, xxxxxxxxb = don't care 10pppprrrrrrrrrrb where: ppppb = register address ADDR0c, rrrrrrrrrrb = register content
Write 8 bit register 10ppppqqrrrrrrrrb where: ppppb = register address ADDR0, qqb = register address ADDR1, rrrrrrrrb = new register content 0dddddddddddddddb (Standard Diagnosis)
Read 8 bit registers 01ppppqqxxxxxx10b where: ppppb = register address ADDR0, qqb = register address ADDR1, xxxxxxb = don't care 10ppppqqrrrrrrrrb where: ppppb = register address ADDR0c, qqb = register address ADDR1, rrrrrrrrb = register content

“p” = address bits for ADDR0 field, “q” = address bit for ADDR1 field, “r” = register content, “d” = diagnostic bit