SLVSGI9A october 2022 – july 2023 DRV8411A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Whenever the voltage on the VM pin falls below the UVLO falling threshold voltage, VUVLO, all circuitry in the device is disabled, the output FETS are disabled, and all internal logic is reset. Normal operation resumes when the VVM voltage rises above the UVLO rising threshold as shown in Figure 9-7. The nFAULT pin is driven low during an undervoltage condition and is released after operation starts again.
When VVM is close to 0 V, the internal circuitry may not bias properly, and the open-drain pull-down on the nFAULT pin may release.