SLVSGI9B October   2022  – July 2024 DRV8411A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
  8. 7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 External Components
    4. 8.4 Feature Description
      1. 8.4.1 Bridge Control
        1. 8.4.1.1 Parallel Bridge Interface
      2. 8.4.2 Current Sense and Regulation
        1. 8.4.2.1 Current Sensing
        2. 8.4.2.2 Current Regulation
      3. 8.4.3 Protection Circuits
        1. 8.4.3.1 Overcurrent Protection (OCP)
        2. 8.4.3.2 Thermal Shutdown (TSD)
        3. 8.4.3.3 Undervoltage Lockout (UVLO)
    5. 8.5 Device Functional Modes
      1. 8.5.1 Active Mode
      2. 8.5.2 Low-Power Sleep Mode
      3. 8.5.3 Fault Mode
    6. 8.6 Pin Diagrams
      1. 8.6.1 Logic-Level Inputs
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Typical Application
        1. 9.1.1.1 Stepper Motor Application
          1. 9.1.1.1.1 Design Requirements
          2. 9.1.1.1.2 Detailed Design Procedure
            1. 9.1.1.1.2.1 Stepper Motor Speed
            2. 9.1.1.1.2.2 Current Regulation
            3. 9.1.1.1.2.3 Stepping Modes
              1. 9.1.1.1.2.3.1 Full-Stepping Operation
              2. 9.1.1.1.2.3.2 Half-Stepping Operation with Fast Decay
              3. 9.1.1.1.2.3.3 Half-Stepping Operation with Slow Decay
          3. 9.1.1.1.3 Application Curves
        2. 9.1.1.2 Dual BDC Motor Application
          1. 9.1.1.2.1 Design Requirements
          2. 9.1.1.2.2 Detailed Design Procedure
            1. 9.1.1.2.2.1 Motor Voltage
            2. 9.1.1.2.2.2 Current Regulation
          3. 9.1.1.2.3 Application Curves
        3. 9.1.1.3 Thermal Considerations
          1. 9.1.1.3.1 Maximum Output Current
          2. 9.1.1.3.2 Power Dissipation
          3. 9.1.1.3.3 Thermal Performance
            1. 9.1.1.3.3.1 Steady-State Thermal Performance
            2. 9.1.1.3.3.2 Transient Thermal Performance
    2. 9.2 Power Supply Recommendations
      1. 9.2.1 Bulk Capacitance
      2. 9.2.2 Power Supply and Logic Sequencing
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PWP|16
  • RTE|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DRV8411A PWP or DYZ Package16-Pin HTSSOPTop ViewFigure 5-1 PWP or DYZ Package16-Pin HTSSOPTop View
DRV8411A RTE Package16-Pin WQFNTop ViewFigure 5-2 RTE Package16-Pin WQFNTop View
PIN TYPE(1) DESCRIPTION
NAME RTE PWP, DYZ
AIN1 14 16 I H-bridge control input for full bridge A (AOUT1, AOUT2). See Section 8.4.1. Internal pulldown resistor.
AIN2 13 15 I H-bridge control input for full bridge A (AOUT1, AOUT2). See Section 8.4.1. Internal pulldown resistor.
AIPROPI 12 14 O Analog current output proportional to load current for full bridge A (AOUT1, AOUT2). See Section 8.4.2.
AOUT1 16 2 O Bridge A output 1
AOUT2 2 4 O Bridge A output 2
BIN1 7 9 I H-bridge control input for full bridge B (BOUT1, BOUT2). See Section 8.4.1. Internal pulldown resistor.
BIN2 8 10 I H-bridge control input for full bridge B (BOUT1, BOUT2). See Section 8.4.1. Internal pulldown resistor.
BIPROPI 9 11 O Analog current output proportional to load current for full bridge B (BOUT1, BOUT2). See Section 8.4.2.
BOUT1 5 7 O Bridge B output 1
BOUT2 3 5 O Bridge B output 2
GND 11 13 PWR Device ground. Connect to system ground.
nFAULT 6 8 OD Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation. See Section 8.4.3.
PAD — — — Thermal pad. Connect to system ground.
PGNDA 1 3 PWR Device power ground for full bridge A (AOUT1, AOUT2). Connect to system ground.
PGNDB 4 6 PWR Device power ground for full bridge B (BOUT1, BOUT2). Connect to system ground.
VM 10 12 PWR 1.65-V to 11-V power supply input. Connect a 0.1-µF bypass capacitor to ground, as well as sufficient Bulk Capacitance rated for VM.
VREF 15 1 I External reference voltage input to set internal current regulation limit..See Section 8.4.2.
(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain