SLVSGI9A october 2022 – july 2023 DRV8411A
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES (VM) | ||||||
IVMQ | VM sleep mode current | VVM = 5 V, TJ = 27°C | 4 | 40 | nA | |
IVM | VM active mode current | xIN1 = 3.3 V, xIN2 = 0 V, VVM = 5 V | 2.3 | 4 | mA | |
tWAKE | Turnon time | Sleep mode to active mode delay | 100 | μs | ||
tAUTOSLEEP | Autosleep turnoff time | Active mode to autosleep mode delay | 0.7 | 1.5 | ms | |
LOGIC-LEVEL INPUTS (nSLEEP, AIN1, AIN2, BIN1, BIN2) | ||||||
VIL | Input logic low voltage | 0 | 0.4 | V | ||
VIH | Input logic high voltage | 1.45 | 5.5 | V | ||
VHYS_nSLEEP | nSLEEP Input hysteresis | 100 | mV | |||
VHYS_logic | Logic Input hysteresis (except nSLEEP) | 50 | mV | |||
IIL | Input logic low current | VxINx = 0 V | -1 | 1 | µA | |
IIH | Input logic high current | VxINx = 5 V | 20 | 70 | µA | |
RPD | Input pulldown resistance | 100 | kΩ | |||
tDEGLITCH | Input logic deglitch | 50 | ns | |||
OPEN-DRAIN OUTPUTS (nFAULT) | ||||||
VOL | Output logic low voltage | IOD = 5 mA | 0.3 | V | ||
IOZ | Output logic high current | VOD = 5 V | -1 | 1 | µA | |
DRIVER OUTPUTS (AOUT1, AOUT2, BOUT1, BOUT2) | ||||||
RHS_DS(ON) | High-side MOSFET on resistance | IOUTx = 0.2 A | 200 | mΩ | ||
RLS_DS(ON) | Low-side MOSFET on resistance | IOUTx = -0.2 A | 200 | mΩ | ||
VSD | Body diode forward voltage | IOUTx = -0.5 A | 1 | V | ||
tRISE | Output rise time | VOUTx rising from 10% to 90% of VVM, VVM = 5 V | 100 | ns | ||
tFALL | Output fall time | VOUTx falling from 90% to 10% of VVM, VVM = 5 V | 50 | ns | ||
tPD | Input to output propagation delay | Input crosses 0.8 V to VOUTx = 0.1×VVM, IOUTx = 1 A | 600 | ns | ||
tDEAD | Output dead time | 400 | ns | |||
CURRENT SENSE AND REGULATION | ||||||
AIPROPI | Current mirror scaling factor | 200 | µA/A | |||
AERR | Current mirror total error | IOUT = 1 A, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V | -6 | 6 | % | |
IOUT = 1 A, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V | -9 | 6 | % | |||
tOFF | Current regulation off time | 20 | µs | |||
tBLANK | Current regulation blanking time | 1.8 | µs | |||
tDELAY | Current sense delay time | 2 | µs | |||
tDEG | Current regulation deglitch time | 1 | µs | |||
PROTECTION CIRCUITS | ||||||
VUVLO | Supply undervoltage lockout (UVLO) | Supply rising | 1.6 | V | ||
Supply falling | 1.3 | V | ||||
VUVLO_HYS | Supply UVLO hysteresis | Rising to falling threshold | 100 | mV | ||
tUVLO | Supply undervoltage deglitch time | VVM falling to OUTx disabled | 10 | µs | ||
IOCP | Overcurrent protection trip point | 4 | A | |||
tOCP | Overcurrent protection deglitch time | 4.2 | µs | |||
tRETRY | Overcurrent protection retry time | 1.6 | ms | |||
TTSD | Thermal shutdown temperature | 153 | 193 | °C | ||
THYS | Thermal shutdown hysteresis | 18 | °C |