SLVSI22 August   2025 DRV8844A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Stage
      2. 6.3.2 Logic Inputs
      3. 6.3.3 Bridge Control
      4. 6.3.4 Charge Pump
      5. 6.3.5 Protection Circuits
        1. 6.3.5.1 Overcurrent Protection (OCP)
        2. 6.3.5.2 Thermal Shutdown (TSD)
        3. 6.3.5.3 Undervoltage Lockout (UVLO)
      6. 6.3.6 CLR_FAULT and nSLEEP Operation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Application Information
      1. 7.2.1 Driving Solenoid Loads
      2. 7.2.2 Driving Stepper Motor
      3. 7.2.3 Driving Brushed DC motor
    3. 7.3 Power Supply Recommendations
      1. 7.3.1 Bulk Capacitance
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
        1. 7.4.3.1 Heatsinking
      4. 7.4.4 Power Dissipation
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Community Resources
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Layout Guidelines

  • The VM pins are bypassed to VNEG pins using low-ESR ceramic bypass capacitors with a recommended value of 0.1µF rated for VM. The capacitors are placed as close to the VM pins as possible with a thick trace or ground plane connection to the device VNEG pins.
  • A low-ESR ceramic capacitor must be placed in between the CP1 and CP2 pins. A value of 0.01µF rated for VM is recommended. Place this component as close to the pins as possible.
  • A low-ESR ceramic capacitor must be placed in between the VM and VCP pins. A value of 0.1µF rated for 16V is recommended. Place this component as close to the pins as possible.
  • Bypass the V3P3OUT pin to ground with a low-ESR ceramic capacitor. A value of 0.47µF rated for 6.3V is recommended. Place this bypassing capacitor as close to the pin as possible.
  • In general, inductance between the power supply pins and decoupling capacitors must be avoided.
  • The thermal PAD of the package must be connected to system ground.
    • Try to use a big unbroken single ground plane for the whole system / board. The ground plane can be made at bottom PCB layer. Figure 7-8 shows an example of temperature rise from constricted versus continuous ground pours underneath the driver.
    • To minimize the impedance and inductance, the traces from ground pins are as short and wide as possible, before connecting to bottom layer ground plane through vias.
    • Multiple vias are suggested to reduce the impedance.
    • Try to clear the space around the device as much as possible especially at bottom PCB layer to improve the heat spreading.
    • Single or multiple internal ground planes connected to the thermal PAD also help spread the heat and reduce the thermal resistance.
  • For more layout guidelines and best practices see the Application Note Best Practices for Board Layout of Motor Drivers.
DRV8844A Broken Ground vs Continuous Ground Pour Heat Map Figure 7-8 Broken Ground vs Continuous Ground Pour Heat Map