SNIS133E September   2003  – February 2024 LM95010

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Operating Ratings
    3. 5.3 DC Electrical Characteristics
    4. 5.4 AC Electrical Characteristics
    5. 5.5 Typical Performance Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  SensorPath BUS SWD
      2. 6.3.2  SensorPath BIT SIGNALING
      3. 6.3.3  Bus Inactive
      4. 6.3.4  Data Bit 0 and 1
      5. 6.3.5  Start Bit
      6. 6.3.6  Attention Request
      7. 6.3.7  Bus Reset
      8. 6.3.8  SensorPath BUS TRANSACTIONS
      9. 6.3.9  Bus Reset Operation
      10. 6.3.10 Read Transaction
      11. 6.3.11 Write Transaction
      12. 6.3.12 Read and Write Transaction Exceptions
      13. 6.3.13 Attention Request Transaction
  8. 7 Register Set
    1. 7.1  Fixed Number Setting
    2. 7.2  Register Set Summary
    3. 7.3  Device Reset Operation
    4. 7.4  Device Number (Addr 00o)
    5. 7.5  Manufacturer ID (Addr 01o)
    6. 7.6  Device ID (Addr 02o)
    7. 7.7  Capabilities Fixed (Addr 03o)
    8. 7.8  Device Status (Addr 04o)
    9. 7.9  Device Control (Addr 05o)
    10. 7.10 Temperature Measurement Function (TYPE - 0001)
    11. 7.11 Operation
    12. 7.12 Temperature Capabilities (Addr 10o)
    13. 7.13 Temperature Data Readout (Addr 11o)
    14. 7.14 Temperature Control (Addr 12o)
    15. 7.15 Conversion Rate (Addr 40o)
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Mounting Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4 Data Bit 0 and 1

All Data Bit signal transfers are started by the master. A Data Bit 0 is indicated by a "short" pulse; a Data Bit 1 is indicated by a longer pulse. The direction of the bit is relative to the master, as follows:

  • Data Write - a Data Bit transferred from the master to the LM95010.
  • Data Read - a Data Bit transferred from the LM95010 to the master.

A master must monitor the bus as inactive before starting a Data Bit (read or Write).

A master initiates a data write by driving the bus active (low level) for the period that matches the data value (tMtr0 or tMtr1 for a write of "0" or "1", respectively). The LM95010 will detect that the SWD becomes active within a period of tSFEdet, and will start measuring the duration of that the SWD is active in order to detect the data value.

A master initiates a data read by driving the bus for a period of tMtr0. The LM95010 will detect that the SWD have become active within a period of tSFEdet. For a data read of "0", the LM95010 will not drive the SWD. For a data read of "1" the LM95010 will start within tSFEdet to drive the SWD low for a period of tSLout1. Both master and LM95010 must monitor the time at which the bus becomes inactive to identify a data read of "0" or "1".

During each Data Bit, both the master and all the LM95010s must monitor the bus (the master for Attention Request and Reset; at the LM95010s for Start Bit, Attention Request and Reset) by measuring the time SWD is active (low). If a Start Bit, Attention Requests or Reset "bit signal" is detected, the current "bit signal" is not treated as a Data Bit.

Note that the bit rate of the protocol varies depending on the data transferred. Thus, the LM95010 has a value of "0" in reserved or unused register bits for bus bandwidth efficiency.