SNAS635F December   2013  – August 2025 LMK00334

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements, Propagation Delay, and Output Skew
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Crystal Power Dissipation vs RLIM
      2. 7.3.2 Clock Inputs
      3. 7.3.3 Clock Outputs
        1. 7.3.3.1 Reference Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC and VCCO Power Supplies
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Driving the Clock Inputs
        2. 8.2.1.2 Crystal Interface
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Termination and Use of Clock Drivers
        2. 8.2.2.2 Termination for DC-Coupled Differential Operation
        3. 8.2.2.3 Termination for AC-Coupled Differential Operation
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Current Consumption and Power Dissipation Calculations
        1. 8.3.1.1 Power Dissipation Example: Worst-Case Dissipation
      2. 8.3.2 Power Supply Bypassing
        1. 8.3.2.1 Power Supply Ripple Rejection
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Management
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

Unless otherwise specified: VCC = 3.3V ± 5%, VCCO = 3.3V ± 5%, 2.5V ± 5%, –40°C ≤ TA ≤ 85°C, CLKin driven differentially, input slew rate ≥ 3V/ns. Typical values represent the most likely parametric norms at VCC = 3.3V, VCCO = 3.3V, TA = 25°C, and at the Recommended Operation Conditions at the time of product characterization; because of this, typical values are not ensured. (1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT CONSUMPTION (1)
ICC_CORE Core supply current, all outputs disabled CLKinX selected 8.5 10.5 mA
OSCin selected 10 13.5 mA
ICC_HCSL 50 58.5 mA
ICC_CMOS 3.5 5.5 mA
ICCO_HCSL Additive output supply current, HCSL banks enabled Includes output bank bias and load currents for both banks, RT = 50Ω on all outputs 65 81.5 mA
ICCO_CMOS Additive output supply current, LVCMOS output enabled 200MHz, CL = 5pF VCCO = 3.3V ±5% 9 10 mA
VCCO = 2.5V ± 5% 7 8 mA
POWER SUPPLY RIPPLE REJECTION (PSRR)
PSRRHCSL Ripple-induced phase spur level(2)
Differential HCSL Output		 156.25MHz –72 dBc
312.5MHz –63
CMOS CONTROL INPUTS (CLKin_SELn, CLKout_TYPEn, REFout_EN)
VIH High-level input voltage 1.6 VCC V
VIL Low-level input voltage GND 0.4 V
IIH High-level input current VIH = VCC, internal pulldown resistor 50 μA
IIL Low-level input current VIL = 0V, internal pulldown resistor –5 0.1 μA
CLOCK INPUTS (CLKin0/CLKin0*, CLKin1/CLKin1*)
fCLKin Input frequency range(8) Functional up to 400MHz
Output frequency range and timing specified per output type (refer to LVCMOS output specifications)		 DC 400 MHz
VIHD Differential input high voltage CLKin driven differentially Vcc V
VILD Differential input low voltage GND V
VID Differential input voltage swing(3) 0.15 1.3 V
VCMD Differential input CMD common-mode voltage VID = 150mV 0.25 VCC – 1.2 V
VID = 350mV 0.25 VCC – 1.1
VID = 800mV 0.25 VCC – 0.9
VIH Single-ended input IH high voltage CLKinX driven single-ended (AC- or DC-coupled), CLKinX* AC-coupled to GND or externally biased within VCM range VCC V
VIL Single-ended input IL low voltage GND V
VI_SE Single-ended input voltage swing(8) 0.3 2 Vpp
VCM Single-ended input CM common-mode voltage 0.25 VCC – 1.2 V
ISOMUX Mux isolation, CLKin0 to CLKin1 fOFFSET > 50kHz, PCLKinX = 0dBm fCLKin0 = 100MHz –84 dBc
fCLKin0 = 200MHz –82
fCLKin0 = 500MHz –71
fCLKin0 = 1000MHz –65
CRYSTAL INTERFACE (OSCin, OSCout)
FCLK External clock frequency range(8) OSCin driven single-ended, OSCout floating 250 MHz
FXTAL Crystal frequency range Fundamental mode crystal ESR ≤ 200Ω (10 to 30MHz) ESR ≤ 125Ω (30 to 40MHz)(4) 10 40 MHz
CIN OSCin input capacitance 1 pF
HCSL OUTPUTS (CLKoutAn/CLKoutAn*, CLKoutBn/CLKoutBn*)
fCLKout Output frequency range(8) RL = 50Ω to GND, CL ≤ 5pF DC 400 MHz
JitterADD_PCle Additive RMS phase jitter for PCIe 7.0(8)

PCIe Gen 7 filter

 CLKin: 100MHz, slew rate ≥ 3V/ns

3.51

5.45

fs
JitterADD_PCle Additive RMS phase jitter for PCIe 6.0(8)

PCIe Gen 6 filter

 CLKin: 100MHz, slew rate ≥ 3V/ns

5.04

7.78

fs
JitterADD_PCle Additive RMS phase jitter for PCIe 5.0(8)

PCIe Gen 5 filter

 CLKin: 100MHz, slew rate ≥ 3V/ns 7.17

12.8

fs
JitterADD_PCle Additive RMS phase jitter for PCIe 4.0(8) PCIe Gen 4,
PLL BW = 2–5MHz,
CDR = 10MHz		 CLKin: 100MHz, slew rate ≥ 3V/ns

20.3

 30.5

fs
JitterADD_PCle Additive RMS phase jitter for PCIe 3.0(8) PCIe Gen 3,
PLL BW = 2–5MHz,
CDR = 10MHz		 CLKin: 100MHz, slew rate ≥ 3V/ns

20.3

30.5

 fs
JitterADD Additive RMS jitter integration bandwidth 12MHz to 20MHz(5) VCCO = 3.3V,
RT = 50Ω to GND		 CLKin: 100MHz, slew rate ≥ 3V/ns 77 fs
Noise Floor Noise floor fOFFSET ≥ 10MHz(6)(7) VCCO = 3.3V,
RT = 50Ω to GND		 CLKin: 100MHz, slew rate ≥ 3V/ns –161.3 dBc/Hz
DUTY Duty cycle(8) 50% input clock duty cycle 45% 55%
VOH Output high voltage TA = 25°C, DC measurement,
RT = 50Ω to GND		 520 810 920 mV
–150 0.5 150 mV
VOL Output low voltage
VCROSS Absolute crossing voltage(8)(9) RL = 50Ω to GND, CL ≤ 5pF 250 350 460 mV
140 mV
ΔVCROSS Total variation of VCROSS(8)(9)
tR Output rise time 20% to 80%(9)(12) 250MHz, uniform transmission line up to 10 in. with 50Ω characteristic impedance, RL = 50Ω to GND, CL ≤ 5pF 225 400 ps
tF Output fall time 80% to 20%(9)(12) 225 400 ps
LVCMOS OUTPUT (REFout)
fCLKout Output frequency range(8) CL ≤ 5pF DC 250 MHz
JitterADD Additive RMS jitter integration bandwidth 1MHz to 20MHz(5) VCCO = 3.3V,
CL ≤ 5pF		 100MHz, input slew rate ≥ 3V/ns 95 fs
Noise Floor Noise floor fOFFSET ≥ 10MHz(6)(7) VCCO = 3.3V,
CL ≤ 5pF		 100MHz, input slew rate ≥ 3V/ns –159.3 dBc/Hz
DUTY Duty cycle(8) 50% input clock duty cycle 45% 55%
VOH Output high voltage 1mA load VCCO – 0.1 V
VOL Output low voltage 0.1 V
IOH Output high current (source) VO = VCCO / 2 VCCO = 3.3V 28 mA
VCCO = 2.5V 20
VCCO = 3.3V 28 mA
VCCO = 2.5V 20
IOL Output low current (sink)
tR Output rise time 20% to 80%(9)(12) 250MHz, uniform transmission line up to 10 in. with 50Ω characteristic impedance, RL = 50Ω to GND, CL ≤ 5pF 225 400 ps
tF Output fall time 80% to 20%(10)(12) 225 400 ps
tEN Output enable time(10) CL ≤ 5pF 3 cycles
tDIS Output disable time(10) 3 cycles
(1) See Power Supply Recommendations and Thermal Management for more information on current consumption and power dissipation calculations.
(2) Power supply ripple rejection, or PSRR, is defined as the single-sideband phase spur level (in dBc) modulated onto the clock output when a single-tone sinusoidal signal (ripple) is injected onto the VCCO supply. Assuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows: DJ (ps pk-pk) = [ (2 × 10(PSRR / 20)) / (π × fCLK) ] × 1E12
(3) See Differential Voltage Measurement Terminology for definition of VID and VOD voltages.
(4) The ESR requirements stated must be met to verify that the oscillator circuitry has no start-up issues. However, lower ESR values for the crystal is not always necessary to stay below the maximum power dissipation (drive level) specification of the crystal. Refer to Crystal Interface for crystal drive level considerations.
(5) For the 100MHz and 156.25MHz clock input conditions, Additive RMS Jitter (JADD) is calculated using Method #1: JADD = SQRT(JOUT2 - JSOURCE2), where JOUT is the total RMS jitter measured at the output driver and JSOURCE is the RMS jitter of the clock source applied to CLKin. For the 625MHz clock input condition, Additive RMS Jitter is approximated using Method #2: JADD = SQRT(2 × 10dBc/10) / (2 × π × fCLK), where dBc is the phase noise power of the Output Noise Floor integrated from 12kHz to 20MHz bandwidth. The phase noise power can be calculated as: dBc = Noise Floor + 10 × log10(20MHz – 12kHz).
(6) The noise floor of the output buffer is measured as the far-out phase noise of the buffer. Typically this offset is ≥ 10MHz, but for lower frequencies this measurement offset can be as low as 5MHz due to measurement equipment limitations.
(7) Phase noise floor degrades as the clock input slew rate is reduced. Compared to a single-ended clock, a differential clock input (LVPECL, LVDS) is less susceptible to degradation in noise floor at lower slew rates due to the common-mode noise rejection. However, TI recommends using the highest possible input slew rate for differential clocks to achieve the best noise floor performance at the device outputs.
(8) Specification is verified by characterization and is not tested in production.
(9) AC timing parameters for HCSL or CMOS are dependent on output capacitive loading.
(10) Output Enable Time is the number of input clock cycles required for the output to be enabled after REFout_EN is pulled high. Similarly, Output Disable Time is the number of input clock cycles required for the output to be disabled after REFout_EN is pulled low. The REFout_EN signal must have an edge transition much faster than that of the input clock period for accurate measurement.
(11) Output skew is the propagation delay difference between any two outputs with identical output buffer type and equal loading while operating at the same supply voltage and temperature conditions.
(12) Parameter is specified by design, not tested in production.