SNAS918 May   2025 LMK5C23208A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
    2. 7.2 Output Clock Test Configurations
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
      1. 8.2.1 PLL Architecture Overview
      2. 8.2.2 DPLL
        1. 8.2.2.1 Independent DPLL Operation
        2. 8.2.2.2 Cascaded DPLL Operation
        3. 8.2.2.3 APLL Cascaded With DPLL
      3. 8.2.3 APLL-Only Mode
    3. 8.3 Feature Description
      1. 8.3.1  Oscillator Input (XO)
      2. 8.3.2  Reference Inputs
      3. 8.3.3  Clock Input Interfacing and Termination
      4. 8.3.4  Reference Input Mux Selection
        1. 8.3.4.1 Automatic Input Selection
        2. 8.3.4.2 Manual Input Selection
      5. 8.3.5  Hitless Switching
        1. 8.3.5.1 Hitless Switching With Phase Cancellation
        2. 8.3.5.2 Hitless Switching With Phase Slew Control
        3. 8.3.5.3 Hitless Switching With 1PPS Inputs
      6. 8.3.6  Gapped Clock Support on Reference Inputs
      7. 8.3.7  Input Clock and PLL Monitoring, Status, and Interrupts
        1. 8.3.7.1 XO Input Monitoring
        2. 8.3.7.2 Reference Input Monitoring
          1. 8.3.7.2.1 Reference Validation Timer
          2. 8.3.7.2.2 Frequency Monitoring
          3. 8.3.7.2.3 Missing Pulse Monitor (Late Detect)
          4. 8.3.7.2.4 Runt Pulse Monitor (Early Detect)
          5. 8.3.7.2.5 Phase Valid Monitor for 1PPS Inputs
        3. 8.3.7.3 PLL Lock Detectors
        4. 8.3.7.4 Tuning Word History
        5. 8.3.7.5 Status Outputs
        6. 8.3.7.6 Interrupt
      8. 8.3.8  PLL Relationships
        1. 8.3.8.1  PLL Frequency Relationships
          1. 8.3.8.1.1 APLL Phase Frequency Detector (PFD) and Charge Pump
          2. 8.3.8.1.2 APLL VCO Frequency
          3. 8.3.8.1.3 DPLL TDC Frequency
          4. 8.3.8.1.4 DPLL VCO Frequency
          5. 8.3.8.1.5 Clock Output Frequency
        2. 8.3.8.2  Analog PLLs (APLL1, APLL2)
        3. 8.3.8.3  APLL Reference Paths
          1. 8.3.8.3.1 APLL XO Doubler
          2. 8.3.8.3.2 APLL XO Reference (R) Divider
        4. 8.3.8.4  APLL Feedback Divider Paths
          1. 8.3.8.4.1 APLL N Divider With Sigma-Delta Modulator (SDM)
        5. 8.3.8.5  APLL Loop Filters (LF1, LF2)
        6. 8.3.8.6  APLL Voltage-Controlled Oscillators (VCO1, VCO2)
          1. 8.3.8.6.1 VCO Calibration
        7. 8.3.8.7  APLL VCO Clock Distribution Paths
        8. 8.3.8.8  DPLL Reference (R) Divider Paths
        9. 8.3.8.9  DPLL Time-to-Digital Converter (TDC)
        10. 8.3.8.10 DPLL Loop Filter (DLF)
        11. 8.3.8.11 DPLL Feedback (FB) Divider Path
      9. 8.3.9  Output Clock Distribution
      10. 8.3.10 Output Source Muxes
      11. 8.3.11 Output Channel Muxes
      12. 8.3.12 Output Dividers (OD)
      13. 8.3.13 SYSREF/1PPS Output
      14. 8.3.14 Output Delay
      15. 8.3.15 Clock Output Drivers
        1. 8.3.15.1 Differential Output
        2. 8.3.15.2 LVCMOS Output
      16. 8.3.16 Clock Output Interfacing and Termination
      17. 8.3.17 Glitchless Output Clock Start-Up
      18. 8.3.18 Output Auto-Mute During LOL
      19. 8.3.19 Output Synchronization (SYNC)
      20. 8.3.20 Zero-Delay Mode (ZDM)
      21. 8.3.21 DPLL Programmable Phase Delay
      22. 8.3.22 Time Elapsed Counter (TEC)
        1. 8.3.22.1 Configuring TEC Functionality
        2. 8.3.22.2 SPI as a Trigger Source
        3. 8.3.22.3 GPIO Pin as a TEC Trigger Source
          1. 8.3.22.3.1 An Example: Making a Time Elapsed Measurement Using TEC and GPIO1 as Trigger
        4. 8.3.22.4 TEC Timing
        5. 8.3.22.5 Other TEC Behavior
    4. 8.4 Device Functional Modes
      1. 8.4.1 DPLL Operating States
        1. 8.4.1.1 Free-Run
        2. 8.4.1.2 Lock Acquisition
        3. 8.4.1.3 DPLL Locked
        4. 8.4.1.4 Holdover
      2. 8.4.2 Digitally-Controlled Oscillator (DCO) Frequency and Phase Adjustment
        1. 8.4.2.1 DPLL DCO Control
        2. 8.4.2.2 DPLL DCO Relative Adjustment Frequency Step Size
        3. 8.4.2.3 APLL DCO Frequency Step Size
      3. 8.4.3 APLL Frequency Control
      4. 8.4.4 Device Start-Up
        1. 8.4.4.1 Device Power-On Reset (POR)
        2. 8.4.4.2 PLL Start-Up Sequence
        3. 8.4.4.3 Start-Up Options for Register Configuration
        4. 8.4.4.4 GPIO1 and SCS_ADD Functionalities
        5. 8.4.4.5 ROM Page Selection
        6. 8.4.4.6 ROM Detailed Description
        7. 8.4.4.7 EEPROM Overlay
    5. 8.5 Programming
      1. 8.5.1 Memory Overview
      2. 8.5.2 Interface and Control
        1. 8.5.2.1 Programming Through TICS Pro
        2. 8.5.2.2 SPI Serial Interface
        3. 8.5.2.3 I2C Serial Interface
      3. 8.5.3 General Register Programming Sequence
      4. 8.5.4 Steps to Program the EEPROM
        1. 8.5.4.1 Overview of the SRAM Programming Methods
        2. 8.5.4.2 EEPROM Programming With the Register Commit Method
        3. 8.5.4.3 EEPROM Programming With the Direct Writes Method or Mixed Method
        4. 8.5.4.4 Five MSBs of the I2C Address and the EEPROM Revision Number
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Start-Up Sequence
      2. 9.1.2 Power Down (PD#) Pin
      3. 9.1.3 Strap Pins for Start-Up
      4. 9.1.4 Pin States
      5. 9.1.5 ROM and EEPROM
      6. 9.1.6 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
        1. 9.1.6.1 Power-On Reset (POR) Circuit
        2. 9.1.6.2 Power Up From a Single-Supply Rail
        3. 9.1.6.3 Power Up From Split-Supply Rails
        4. 9.1.6.4 Non-Monotonic or Slow Power-Up Supply Ramp
      7. 9.1.7 Slow or Delayed XO Start-Up
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 Power Supply Bypassing
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
      3. 9.5.3 Thermal Reliability
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 Clock Tree Architect Programming Software
        2. 10.1.1.2 Texas Instruments Clocks and Synthesizers (TICS) Pro Software
        3. 10.1.1.3 PLLatinum™ Simulation Tool
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data
    2.     PACKAGING INFORMATION
    3. 12.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

Over Recommended Operating Conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Consumption Characteristics
IDD-XO XO input current consumption XO 3.5 mA
IDD-XO2X Current consumption per XO doubler XO doubler(1) 0.3 mA
IDD-INX Core current consumption per DPLL reference input block IN0 3.6 mA
IN1 3.1 mA
IDD-DPLL Current consumption per DPLL DPLL(2) 55 mA
IDD-APLL1 APLL1 current consumption APLL1  90 mA
IDD-APLL2 APLL2 current consumption APLL2  160 mA
IDD-APLL3 BAW APLL current consumption APLL3, BAW APLL 120 mA
IDD-APLL1 BAW APLL current consumption APLL1, BAW APLL 120 mA
IDD-ANA Analog bias current consumption Analog circuitry from VDD_APLL1_XO supply pin. Always on when device is enabled. 42 mA
IDD-DIG Digital control current consumption Digital control circuitry from VDD_DIG supply pin always on when device is enabled. 34 mA
IDDO-CHDIV Current consumption per channel divider block 12-bit channel divider 20 mA
IDDO-1PPSDIV Current consumption per 1PPS/SYSREF divider block 20-bit 1PPS/SYSREF divider 12 mA
IDDO-DELAY Current consumption per 1PPS/SYSREF analog delay block Analog delay function enabled 10 mA
IDDO-HSDS HSDS current consumption per output driver HSDS buffer (VCM level = s1, Iout = 4mA, 100Ω termination)  19 mA
HSDS buffer (VCM level = s1, Iout = 7mA, 100Ω termination) 22 mA
HSDS buffer (VCM level = s1, Iout = 10mA, 100Ω termination) 25 mA
IDDO-HCSL HCSL current consumption per output driver HCSL output (50Ω termination per side) 30.5 mA
IDD_PD Power-down current consumption Device powered-down, PD# = LOW 90 110 mA
Reference Input Characteristics (INx)
fIN INx frequency range Single-ended input 0.5E–6 200 MHz
Differential input 5 800
VIH Single-ended input high voltage DC-coupled input mode  (3) 1.2 VDD + 0.3 V
VIL Single-ended input low voltage 0.5 V
VIN-SE-PP Single-ended input voltage swing AC-coupled input mode (4) 0.4 2 Vpp
VIN-DIFF-PP Differential input voltage swing AC- or DC- coupled input (5) 0.4 2 Vpp
VICM Input Common Mode DC- coupled differential input (6) 0.1 2 V
dV/dt Input slew rate Single-ended input 0.2 0.5 V/ns
Differential input 0.2 0.5 V/ns
IDC Input Clock Duty Cycle Non 1PPS signal 40 60 %
tPULSE-1PPS 1PPS pulse width for input 1PPS or pulsed signal 100 ns
IIN-DC DC input leakage current Single pin INx_P or INx_N, 50Ω and 100Ω internal terminations disabled, AC coupled mode enabled or disabled –350 350 µA
CIN Input capacitance Single-ended, each pin 2 pF
XO/TCXO Input Characteristics (XO)
fCLK XO input frequency range (7) 10 156.25 MHz
VIH LVCMOS Input high voltage DC-coupled input mode (8) 1.4 VDD + 0.3 V
VIL LVCMOS Input low voltage 0.8 V
VIN-SE Single-ended input voltage swing AC-coupled input mode (9) 0.4 VDD + 0.3 Vpp
dV/dt Input slew rate 0.2 0.5 V/ns
IDC Input duty cycle 40 60 %
IIN-DC DC Input leakage current Single pin XO_P, 50Ω and 100Ω internal terminations disabled –350 350 µA
CIN Input capacitance on each pin 1 pF
CEXT External AC coupling capacitor 10 nF
APLL/VCO Characteristics
fPFD PFD frequency range BAW APLL Fractional feedback divider 110 MHz
APLL1, APLL2 Fractional feedback divider 125 MHz
fVCO1 VCO1 Frequency range APLL1 4800 5350 MHz
fVCO2 VCO2 Frequency range APLL2 5595 5950 MHz
fVCBO VCBO Frequency range APLL3, BAW APLL 2457.35 2457.6 2457.85 MHz
tAPLL1-LOCK APLL1 lock time Time between soft or hard reset and stable APLL1 output. 20 35 ms
tAPLL2-LOCK APLL2 lock time Time between soft or hard reset and stable APLL2 output. 350 460 ms
tBAW APLL-LOCK BAW APLL lock time Time between soft or hard reset and stable BAW APLL output. 12.5 13 ms
HSDS Output Characteristics (OUTx)
fOUT Output frequency range 1E–6 1250 MHz
VOUT-DIFF Differential output swing 2×VOD-HSDS mVpp
VOD-HSDS HSDS output voltage swing fout < 100MHz, Iout = 4mA  350 400 440 mV
fout < 100MHz, Iout = 7mA 625 700 750 mV
fout < 100MHz, Iout = 10mA 900 975 1050 mV
100MHz ≤ fout ≤ 325MHz, Iout = 4mA 335 400 445 mV
100MHz ≤ fout ≤ 325MHz, Iout = 5mA 425 500 575 mV
100MHz ≤ fout ≤ 325MHz, Iout = 6mA 510 600 690 mV
100MHz ≤ fout ≤ 325MHz, Iout = 7mA 595 700 805 mV
100MHz ≤ fout ≤ 325MHz, Iout = 8mA 680 800 920 mV
100MHz ≤ fout ≤ 325MHz, Iout = 9mA 765 900 1035 mV
100MHz ≤ fout ≤ 325MHz, Iout = 10mA 850 1000 1150 mV
325MHz < fout ≤ 800MHz, Iout = 4mA 300 350 400 mV
325MHz < fout ≤ 800MHz, Iout = 7mA 580 640 700 mV
325MHz < fout ≤ 800MHz, Iout = 10mA 800 865 940 mV
800MHz < fout ≤ 1250MHz, Iout = 4mA 235 320 400 mV
800MHz < fout ≤ 1250MHz, Iout = 7mA 480 625 740 mV
800MHz < fout ≤ 1250MHz, Iout = 10mA 600 800 1000 mV
VOH Output voltage high VOL + VOD mVpp
VOL Output voltage low VCM level = s1 50 150 250 mV
VCM level = s2+3 300 470 720 mV
VCM Output common mode voltage VCM level = s1 or s2+3 VOL + VOD/2 V
VCM level = s2, Iout = 4mA 0.6 0.7 0.8 V
VCM level = s3, Iout = 4mA 1.125 1.25 1.375 V
tSKEW Output skew (12) Same APLL, same post divider and channel divider values, same bank 50 ps
Same APLL, same post divider and channel divider values, between banks 80 ps
tR/tF Rise/Fall time fOUT < 100MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2pF 200 250 350 ps
100MHz ≤ fOUT ≤ 325MHz, 20% to 80%, Iout ≥ 8mA, OUT_x_CAP_EN = 0, CL = 2pF 165 225 260 ps
100MHz ≤ fOUT ≤ 325MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2pF 175 230 300 ps
325MHz < fOUT ≤ 800MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2pF 150 215 285 ps
800MHz < fOUT ≤ 1250MHz, 20% to 80%, OUT_x_CAP_EN = 0, CL = 2pF 120 205 250 ps
ODC Output duty cycle 48 52 %
HCSL Output Characteristics (OUTx)
fOUT Output frequency range HSCL output mode 25 100 650 MHz
VOL Output voltage low –150 0 150 mV
VOH Output voltage high 600 750 900 mV
VMIN Output voltage minimum Including undershoot –300 0 150 mV
VMAX Output voltage maximum Including overshoot 600 750 1150 mV
dV/dt Differential output slew rate ±150mV around center point, OUT_x_CAP_EN = 1, CL= 2pF 2 4 V/ns
dV/dt Differential output slew rate ±150mV around center point,OUT_x_CAP_EN = 0, CL= 2pF 3 5 V/ns
tSKEW Output skew (12) Same APLL, same post divider and channel divider values, same bank 50 ps
Same APLL, same post divider and channel divider values, between banks 80 ps
VCROSS Absolute voltage crossing point fOUT = 100MHz 300 500 mV
ΔVCROSS Voltage crossing point variation fOUT = 100MHz 75 mV
ODC Output duty cycle 45 55 %
1.8V LVCMOS Output Characteristics (OUT0, OUT1)
fOUT Output frequency range 1E–6 200 MHz
VOH Output high voltage IOH = -2mA 1.5 V
VOL Output low voltage IOL = 2mA 0.2 V
tR/tF Output rise/fall time 20% to 80% 150 ps
tSK Output-to-output skew OUT0_P, OUT0_N, OUT1_P, OUT1_N with same polarity, same APLL post divider and output divider values. Same polarity and output type (LVCMOS) 60 ps
Same APLL, same post divider and output divider values. Skew between LVCMOS and differential outputs 0.7 1 1.3 ns
ODC Output duty cycle 45 55 %
ROUT Output impedance 54 64 75 Ω
2.65V LVCMOS Output Characteristics (OUT0, OUT1)
fOUT Output frequency range 1E–6 200 MHz
VOH Output high voltage IOH = -2mA 2.3 V
VOL Output low voltage IOL = 2mA 0.2 V
tR/tF Output rise/fall time 20% to 80% 150 ps
tSK Output-to-output skew OUT_P, OUT0_N, OUT1_P, OUT1_N with same polarity, same APLL post divider and output divider values. Same polarity and output type (LVCMOS) 60 ps
Same APLL, same post divider and output divider values. Skew between LVCMOS and differential outputs 0.7 1.0 1.3 ns
PNFLOOR Output phase noise floor
(fOFFSET > 10MHz)		 25MHz –155 dBc/Hz
ODC Output duty cycle 45 55 %
ROUT Output impedance 40 50 65 Ω
3.3V LVCMOS GPIO Clock Output Characteristics (GPIO0, GPIO1, GPIO2)
fOUT Maximum output frequency GPIO1, GPIO2  25 MHz
VOH Output high voltage IOH= 2mA 2.4 V
VOL Output low voltage IOL= 2mA 0.4 V
IIH Input high current VIN = VDD 100 µA
IIL Output low current VIN = 0V -100 µA
tR/tF Output rise/fall time 20% to 80%, 1kΩ to GND 0.5 1.3 2.6 ns
tSK Output-to-output skew GPIO1, GPIO2 output skew compared to OUT0_P, OUT0_N, OUT1_P, OUT1_N CMOS outputs. GPIOx_SEL = 115
fout = 100kHz		 7.5 11 ns
ODC Output duty cycle 45 55 %
ROUT Output impedance 35 42 50 Ω
PLL Output Clock Noise Characteristics
RJBAW APLL 12kHz to 20MHz integrated RMS jitter for BAW APLL outputs XO = 48MHz, fout = 1222.8MHz,  post divider P1APLL3 = 2, HSDS output  VOD ≥ 800mV  45 fs
XO = 48MHz, fout = 614.4MHz,  post divider P1APLL3 = 4, HSDS output  VOD ≥ 800mV 35 50 fs
XO = 48MHz, fout = 491.52MHz,  post divider P1APLL3 = 5,  HSDS output  VOD ≥ 800mV  40 57 fs
XO = 48MHz, fout = 245.76MHz,  post divider  P1APLL3 = 10, HSDS output  VOD ≥ 800mV 45 64 fs
XO = 48MHz, fout = 245.76MHz,  bypass post divider P1APLL3 = 1, HSDS output  VOD ≥ 800mV (10) 50 62 fs
XO = 48MHz, fout = 122.88MHz,  bypass post divider P1APLL3 = 1, HSDS output  VOD ≥ 800mV (10) 55 86 fs
XO = 48MHz, fout = 245.76MHz, HSDS output, all VOD levels 50 80 fs
XO = 48MHz, fout = 122.88MHz, HSDS output, all VOD levels 60 90 fs
RJAPLL2 12kHz to 20MHz integrated RMS jitter for APLL2 outputs XO = 48MHz, fout = 153.6MHz (VCO2 = 5836.8MHz), 155.52MHz (VCO2 = 5598.72MHz), 174.703084MHz (VCO2 = 5765.2 MHz) or 184.32MHz (VCO2 = 5898.24MHz) from APLL2.
HSDS output , VOD ≥ 800mV from OUT5, OUT6, OUT3. 156.25MHz from BAW APLL output in all other output banks.		 110 150 fs
XO = 48MHz,  fout = 161.1328125MHz or 322.265625MHz (VCO2 = 5800.78125MHz), or 212.5MHz (VCO2 = 5950MHz) from APLL2. 
HSDS output , VOD ≥ 800mV from OUT5, OUT6. 156.25MHz from BAW APLL output in all other output banks.		 110 150 fs
XO = 48MHz,  fout = 156.25MHz or 125MHz (VCO2 = 5625MHz), or 100MHz (VCO2 = 5600MHz) from APLL2.  HSDS output , VOD ≥ 800mV from OUT5, OUT6, OUT3. 156.25MHz from BAW APLL output in all other output banks. 110 150 fs
RJAPLL1 12kHz to 20MHz integrated RMS jitter for APLL1 outputs XO = 48MHz, fout ≥ 100MHz, HSDS output buffer VOD ≥ 800mV 200 300 fs
PSNRVDDO_0_1 Power supply noise rejection VDDO_0_1 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -105 dBc
PSNRVDDO_2 Power supply noise rejection VDDO_2 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -105 dBc
PSNRVDDO_3_4 Power supply noise rejection VDDO_3_4 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -110 dBc
PSNRVDDO_5_6 Power supply noise rejection VDDO_5_6 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -110 dBc
PSNRVDDO_7 Power supply noise rejection VDDO_7 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -110 dBc
PSNRVDD_APLL1_XO Power supply noise rejection VDD_APLL1_XO Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -100 dBc
PSNRVDD_APLL2 Power supply noise rejection VDD_APLL2 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -105 dBc
PSNRVDD_APLL3 Power supply noise rejection VDD_APLL3 Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -105 dBc
PSNRVDD_DIG Power supply noise rejection VDD_DIG Vcc = 3.3V, VN = 50mVpp, HSDS, LVDS or AC-LVPECL outputs. (11) -120 dBc
PCIe Jitter Characteristics
JPCIE-Gen1-CC PCIe Gen 1 (2.5 GT/s) Common Clock jitter APLLx output, 3x noise folding 0.8 5 ps p-p
JPCIE-Gen2-CC PCIe Gen 2 (5.0 GT/s) Common Clock jitter APLLx output, 3x noise folding 85 250 fs RMS
JPCIe-Gen3-CC PCIe Gen 3 (8 GT/s) Common Clock jitter APLLx output, 3x noise folding 25 100 fs RMS
JPCIe-Gen4-CC PCIe Gen 4 (16 GT/s) Common Clock jitter APLLx output, 3x noise folding 25 100 fs RMS
JPCIe-Gen5-CC PCIe Gen 5 (64 GT/s) Common Clock jitter APLLx output, 3x noise folding 9 50 fs RMS
JPCIe-Gen6-CC PCIe Gen 6 (32 GT/s) Common Clock jitter APLLx output, 3x noise folding 6 40 fs RMS
DPLL Characteristics
fTDC TDC rate range for DPLLx 1E–6 26 MHz
dφ/dt Phase slew during switchover Programmable range 695 ns/s
DPLL-BW DPLL loop bandwidth Programmable loop bandwidth(16) 1E–3 4000 Hz
JPK DPLL closed-loop jitter peaking 0.1 dB
JTOL Jitter tolerance Compliant with G.8262 Options 1 and 2. Jitter modulation = 10Hz, 25.78152Gbps line rate 6455 UI p-p
DCO Characteristics
fDCO-DPLL DPLL DCO frequency tuning range DPLLx -200 200 ppm
fDCO-APLL DCO frequency tuning range BAW APLL in holdover or APLL only operation. -200 200 ppm
APLL2, APLL1in holdover or APLL only operation. -1000 1000 ppm
Zero-Delay Mode (ZDM) Characteristics
fOUT-ZDM Output frequency range with ZDM enabled DPLL3: OUT0 1E–6 1250 MHz
fOUT-ZDM Output frequency range with ZDM enabled DPLL2: OUT0 1E–6 700 MHz
tDLY-ZDM Input-to-output propagation delay with ZDM enabled OUT0, fIN ≤ fTDC_MAX, fOUT ≤ fTDC_MAX, DPLLx_PH_OFFSET = 172500 150 ps
tDLY-VAR-ZDM Input-to-output propagation delay variation with ZDM enabled OUT0, fIN ≤ fTDC_MAX, fOUT ≤ fTDC_MAX, DPLLx_PH_OFFSET = 0 65 ±ps
1PPS Reference Characteristics
tDPLL_FL DPLL frequency lock time with 1PPS reference XO = 48MHz, initial error = ±25ppb, -180° ≤ Θ ≤ 180°. DPLL LBW = 10mHz, frequency lock Δfout ≤ ±4.6ppm 5 6 s
tDPLL_PL DPLL phase lock time with 1PPS reference XO = 48MHz, initial error = ±25ppb, -180° ≤ Θ ≤ 180°. DPLL LBW = 10mHz,  DPLL LBW = 10mHz, phase lock ≤ ±100ns 34 38 s
Hitless Switching Characteristics
tHIT Phase transient during switchover INx = 1Hz, INy = 1Hz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 10mHz. 4 ± ps
INx = 8kHz, INy = 8kHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1Hz 19 ± ps
Nx = 25MHz, INy = 25MHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1Hz 1.8 ± ps
fHIT Frequency transient during switchover INx = 1Hz,  INy = 1Hz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 10mHz 0.85 ± ppb
INx = 8kHz, INy = 8kHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1Hz 0.45 ± ppb
INx = 25MHz,  INy = 25MHz, frequency locked. INx and INy relative phase offset -180° ≤ Θ ≤ 180°. DPLL LBW = 1Hz 0.63 ± ppb
Programmable Output Delay Characteristics
tANA-DLY Analog delay step size (13) BAW APLL = 2457.6MHz, VCO post-divider = 2, 0.5x range scale, 1Hz ≤ OUTx  ≤ 122.88MHz, ANA_DELAY_LINEARITY_CODE = 2 13.13 ps
BAW APLL = 2457.6MHz, VCO post-divider= 1, 2x range scale, 1Hz ≤ OUTx  ≤ 122.88MHz, ANA_DELAY_LINEARITY_CODE = 5 26.25 ps
APLL2 = 5625.0MHz, VCO post-divider = 3, 1x range scale, 1Hz ≤ OUTx  ≤ 156.25MHz, ANA_DELAY_LINEARITY_CODE = 3 17.2 ps
APLL2= 5625.0MHz, VCO post-divider = 4; 1x range scale, 1Hz ≤ OUTx  ≤ 156.25MHz, ANA_DELAY_LINEARITY_CODE = 4 22.9 ps
tANA-DLY-ERR Analog delay step size error BAW APLL = 2457.6MHz, VCO post-divider = 2, 0.5x range scale, 1Hz ≤ OUTx  ≤ 122.88MHz, ANA_DELAY_LINEARITY_CODE = 2 -6.56 6.56 ps
BAW APLL = 2457.6MHz, VCO post-divider= 1, 2x range scale, 1Hz ≤ OUTx  ≤ 122.88MHz, ANA_DELAY_LINEARITY_CODE = 5 -13.13 13.13 ps
APLL2 = 5625.0MHz, VCO post-divider = 3, 1x range scale, 1Hz ≤ OUTx  ≤ 156.25MHz, ANA_DELAY_LINEARITY_CODE = 3 -8.6 8.6 ps
APLL2 = 5625.0MHz, VCO post-divider = 4; 1x range scale, 1Hz ≤ OUTx  ≤ 156.25MHz, ANA_DELAY_LINEARITY_CODE = 4 -11.45 11.45 ps
tANA-DLY-RANGE Analog delay range 31 × tANA-DLY ps
tANA-DLY-ACC Analog delay accuracy Analog delay absolute accuracy for any setting N = 0 to 31 across analog delay range. Worst case error of actual value relative to expected value N × tANA-DLY-STEP for ANA_DELAY_LINEARITY_CODE = 3, 4, 5 -25 25 ps
tANA-DLY-LIN Analog delay linearity (14) ANA_DELAY_LINEARITY_CODE = 2 333 450 ps
ANA_DELAY_LINEARITY_CODE = 3 450 600 ps
ANA_DELAY_LINEARITY_CODE = 4 600 750 ps
ANA_DELAY_LINEARITY_CODE = 5 750 1050 ps
tDIG-DLY Digital delay step size VCO post-divider frequency output = 2457.6MHz, half step setting 196.6 ps
VCO post-divider frequency output = 2457.6MHz, full step setting 786.4 ps
3-Level Logic Input Characteristics (GPIO0, GPIO1, GPIO2, SCS_ADD)
VIH Input high voltage 1.4 V
VIM Input mid voltage 0.6 0.95 V
VIM Input mid voltage self-bias Input floating with internal bias and PD# pulled low 0.7 0.9 V
RIM-PD Internal pulldown resistor for mid level self-bias (15) 145 163 180 kΩ
RIM-PU Internal pullup for mid level self-bias (15) 470 526 580 kΩ
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD –40 40 µA
IIL Input low current VIL = GND –40 40 µA
CIN Input capacitance 2 pF
2-Level Logic Input Characteristics (PD#, SCK, SDIO, SCS_ADD; GPIO0, GPIO1 and GPIO2 after power up)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.4 V
IIH Input high current VIH = VDD, except PD# –40 40 µA
IIL Input low current VIL = GND, except PD# –40 40 µA
IIH Input high current VIH = VDD, PD# with internal 200kΩ pull-up –57 24 µA
IIL Input low current VIL = GND, PD# with internal 200kΩ pull-up –57 24 µA
tWIDTH Input pulse width for GPIO SYNC, SYSREF request, TEC trigger, DPLL input selection, FDEV trigger and FDEV_dir Monotonic edges 200 ns
CIN Input capacitance 2 pF
Logic Output Characteristics (GPIO0, GPIO1, GPIO2, SDIO)
VOH Output high voltage IOH = 1mA 2.4 V
VOL Output low voltage IOL = 1mA 0.4 V
tR/tF Output rise/fall time 20% to 80%, LVCMOS mode, 1kΩ to GND 500 ps
Open Drain Output (GPIO0, GPIO1, GPIO2, SDA)
VOL Output Low Level IOL = 3mA 0.3 V
IOL = 6mA 0.6 V
IOH Output Leakage Current -15 15 µA
SPI Timing Requirements (SDIO, SCK, SCS_ADD)
fSCK SPI clock rate 20 MHz
SPI clock rate; during SRAM read and write operations 5 10 MHz
t1 SCS to SCK setup time (start communication cycle) 10 ns
t2 SDI to SCK setup time 10 ns
t3 SDI to SCK hold time 10 ns
t4 SCK high time 25 ns
t5 SCK low time 25 ns
t6 SCK to SDO valid read-back data 20 ns
t7 SCS pulse width 20 ns
t8 SCK to SCS setup time (end communication cycle) 10 ns
I2C Timing Requirements (SDA, SCL)
VIH Input high voltage 1.2 V
VIL Input low voltage 0.5 V
IIH Input leakage –15 15 µA
CIN Input capacitance 2 pF
VOL Output low voltage IOL = 3mA 0.3 V
VOL Output low voltage IOL = 6mA 0.6 V
fSCL I2C clock rate Standard 100 kHz
Fast mode 400
tSU(START) START condition setup time SCL high before SDA low 0.6 µs
tH(START) START condition hold time SCL low after SDA low 0.6 µs
tW(SCLH) SCL pulse width high 0.6 µs
tW(SCLL) SCL pulse width low 1.3 µs
tSU(SDA) SDA setup time 100 ns
tH(SDA) SDA hold time SDA valid after SCL low 0 0.9 µs
tR(IN) SDA/SCL input rise time 300 ns
tF(IN) SDA/SCL input fall time 300 ns
tF(OUT) SDA output fall time CBUS ≤ 400pF 300 ns
tSU(STOP) STOP condition setup time 0.6 µs
tBUS Bus free time between STOP and START 1.3 µs
tVD-DAT Data valid time 0.9 µs
tVD-ACK Data valid acknowledge time 0.9 µs
EEPROM Characteristics
nEE-CYC EEPROM programming cycles 100 cycle
tSRAM-R/W EEPROM SRAM read/write time delay between bytes 0 ms
(1) This is the current consumption of one XO doubler. All XO doublers consume the same current.
(2) This is the current consumption of one DPLL. Each DPLL consumes the same current.
(3) REFx_ITYPE = 8 or 12.
(4) REFx_ITYPE = 1, 3 or 5, non-driven input directly tied to GND, capacitor to GND or 50Ω to GND.
(5) REFx_ITYPE = 1, 3 or 5.
(6) Combination of common mode voltage and DC coupled different input voltage must not exceed Absolute Maximum Ratings.
(7) When XO input frequency is greater than the APLL phase detector maximum supported comparison frequency, the APLL R divider must be set to minimum of divide by 2.
(8) Register XO_ITYPE = 8 or 12.
(9) Register XO_ITYPE = 1, 3 or 5
(10) The BAW APLL post divider is bypassed by setting P1BAW APLL = 1. All OUTx are sourced from channel dividers.
(11) PSNR is the single-sideband spur level measured in dBc when sinusoidal noise with amplitude VN and frequency between 100kHz and 10MHz is injected onto VDD and VDDO pins with 1.0µF decoupling capacitance. 
(12) Output dividers are synchronized. SYNC status achieved from power up or SYNC_SW.
(13) Typical analog delay step size based on APLL post-divider output period divided by 31, times the analog delay range scale value 0.5, 1 or 2.
(14) Analog delay linearity typically selected based on the period of the analog delay range, tANA-DLY-RANGE.
(15) Variation of internal pullup resistor tracks variation of pulldown resistor to maintain a consistent mid voltage self-bias ratio.
(16) DPLL loop bandwidth must be less than 1/100 of TDC frequency and less than 1/10 of APLL loop bandwidth.