SLLSFH8B August 2021 – February 2022 MCT8316A
PRODUCTION DATA
#FAULT_CONFIGURATION_FAULT_CONFIGURATION_TABLE_1 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_TABLE_1 should be considered as reserved locations and the register contents should not be modified.
| Address | Acronym | Register Name | Section |
|---|---|---|---|
| 92h | FAULT_CONFIG1 | Fault configuration 1 | #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1 |
| 94h | FAULT_CONFIG2 | Fault configuration 2 | #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2 |
Complex bit access types are encoded to fit into small table cells. #FAULT_CONFIGURATION_FAULT_CONFIGURATION_LEGEND shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
FAULT_CONFIG1 is shown in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1_FIGURE and described in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1_TABLE.
Return to the Summary Table.
Register to configure fault settings1
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PARITY | RESERVED | NO_MTR_DEG_TIME | CBC_ILIMIT_MODE | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CBC_ILIMIT_MODE | LOCK_ILIMIT | LOCK_ILIMIT_MODE | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| LOCK_ILIMIT_MODE | LOCK_ILIMIT_DEG | CBC_RETRY_PWM_CYC | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | MTR_LCK_MODE | LCK_RETRY | |||||
| R/W-0h | R/W-0h | R/W-0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PARITY | R/W | 0h | Parity bit |
| 30 | RESERVED | R/W | 0h | Reserved |
| 29-27 | NO_MTR_DEG_TIME | R/W | 0h | No motor detect deglitch time
0h = 1 ms 1h = 10 ms 2h = 25 ms 3h = 50 ms 4h = 100 ms 5h = 250 ms 6h = 500 ms 7h = 1000 ms |
| 26-23 | CBC_ILIMIT_MODE | R/W | 0h | Cycle by cycle current limit
0h = Automatic recovery next PWM cycle; nFAULT active; driver is in recirculation mode 1h = Automatic recovery next PWM cycle; nFAULT inactive; driver is in recirculation mode 2h = Automatic recovery if VSOX < ILIMIT; nFAULT active; driver is in recirculation mode (Only available with high-side modulation) 3h = Automatic recovery if VSOX < ILIMIT; nFAULT inactive; driver is in recirculation mode (Only available with high-side modulation) 4h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT active; driver is in recirculation mode 5h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT inactive; driver is in recirculation mode 6h = VSOX > ILIMIT is report only but no action is taken 7h = Cycle by Cycle limit is disabled 8h = Cycle by Cycle limit is disabled 9h = Cycle by Cycle limit is disabled Ah = Cycle by Cycle limit is disabled Bh = Cycle by Cycle limit is disabled Ch = Cycle by Cycle limit is disabled Dh = Cycle by Cycle limit is disabled Eh = Cycle by Cycle limit is disabled Fh = Cycle by Cycle limit is disabled |
| 22-19 | LOCK_ILIMIT | R/W | 0h | Lock detection current limit
(Lock detection current limit (A) = LOCK_ILIMIT / CSA_GAIN)
0h = N/A 1h = 0.1 V 2h = 0.2 V 3h = 0.3 V 4h = 0.4 V 5h = 0.5 V 6h = 0.6 V 7h = 0.7 V 8h = 0.8 V 9h = 0.9 V Ah = 1 V Bh = 1.1 V Ch = 1.2 V Dh = 1.3 V Eh = 1.4 V Fh = 1.5 V |
| 18-15 | LOCK_ILIMIT_MODE | R/W | 0h | Lock detection current limit mode
0h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in recirculation mode 2h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high-side brake mode (All high-side FETs are turned ON) 3h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low-side brake mode (All low-side FETs are turned ON) 4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated 5h = Automatic recovery after tLCK_RETRY; Gate driver is in recirculation mode 6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-side brake mode (All high-side FETs are turned ON) 7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-side brake mode (All low-side FETs are turned ON) 8h = Ilimit lock detection is in report only but no action is taken 9h = Ilimit lock detection is disabled Ah = Ilimit lock detection is disabled Bh = Ilimit lock detection is disabled Ch = Ilimit lock detection is disabled Dh = Ilimit lock detection is disabled Eh = Ilimit lock detection is disabled Fh = Ilimit lock detection is disabled |
| 14-11 | LOCK_ILIMIT_DEG | R/W | 0h | Lock detection current limit deglitch time
0h = 1 ms 1h = 2 ms 2h = 5 ms 3h = 10 ms 4h = 25 ms 5h = 50 ms 6h = 75 ms 7h = 100 ms 8h = 250 ms 9h = 500 ms Ah = 1 s Bh = 2.5 s Ch = 5 s Dh = 10 s Eh = 25 s Fh = 50 s |
| 10-8 | CBC_RETRY_PWM_CYC | R/W | 0h | Number of PWM cycles for CBC current limit to retry
0h = 0 1h = 1 2h = 2 3h = 3 4h = 4 5h = 5 6h = 6 7h = 7 |
| 7 | RESERVED | R/W | 0h | Reserved |
| 6-3 | MTR_LCK_MODE | R/W | 0h | Motor lock mode
0h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated 1h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in recirculation mode 2h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in high-side brake mode (All high-side FETs are turned ON) 3h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low-side brake mode (All low-side FETs are turned ON) 4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated 5h = Automatic recovery after tLCK_RETRY; Gate driver is in recirculation mode 6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-side brake mode (All high-side FETs are turned ON) 7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-side brake mode (All low-side FETs are turned ON) 8h = Motor lock detection is in report only but no action is taken 9h = Motor lock detection is disabled Bh = Motor lock detection is disabled Ch = Motor lock detection is disabled Dh = Motor lock detection is disabled Eh = Motor lock detection is disabled Fh = Motor lock detection is disabled |
| 2-0 | LCK_RETRY | R/W | 0h | Lock retry time
0h = 100 ms 1h = 500 ms 2h = 1000 ms 3h = 2000 ms 4h = 3000 ms 5h = 5000 ms 6h = 7500 ms 7h = 10000 ms |
FAULT_CONFIG2 is shown in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2_FIGURE and described in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2_TABLE.
Return to the Summary Table.
Register to configure fault settings2
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| PARITY | LOCK1_EN | LOCK2_EN | LOCK3_EN | LOCK_ABN_SPEED | |||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | |||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| LOSS_SYNC_TIMES | NO_MTR_THR | MAX_VM_MODE | MAX_VM_MOTOR | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| MAX_VM_MOTOR | MIN_VM_MODE | MIN_VM_MOTOR | AUTO_RETRY_TIMES | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| AUTO_RETRY_TIMES | LOCK_MIN_SPEED | ABN_LOCK_SPD_RATIO | ZERO_DUTY_THR | ||||
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | PARITY | R/W | 0h | Parity bit |
| 30 | LOCK1_EN | R/W | 0h | Lock 1 (Abnormal Speed) Enable
0h = Disable 1h = Enable |
| 29 | LOCK2_EN | R/W | 0h | Lock 2 (Loss of Sync) Enable
0h = Disable 1h = Enable |
| 28 | LOCK3_EN | R/W | 0h | Lock 3 (No Motor) Enable
0h = Disable 1h = Enable |
| 27-24 | LOCK_ABN_SPEED | R/W | 0h | Abnormal speed lock threshold
0h = 250 Hz 1h = 500 Hz 2h = 750 Hz 3h = 1000 Hz 4h = 1250 Hz 5h = 1500 Hz 6h = 1750 Hz 7h = 2000 Hz 8h = 2250 Hz 9h = 2500 Hz Ah = 2750 Hz Bh = 3000 Hz Ch = 3250 Hz Dh = 3500 Hz Eh = 3750 Hz Fh = 4000 Hz |
| 23-21 | LOSS_SYNC_TIMES | R/W | 0h | Number of times sync lost for loss of sync lock fault
0h = Trigger after losing sync 2 times 1h = Trigger after losing sync 3 times 2h = Trigger after losing sync 4 times 3h = Trigger after losing sync 5 times 4h = Trigger after losing sync 6 times 5h = Trigger after losing sync 7 times 6h = Trigger after losing sync 8 times 7h = Trigger after losing sync 9 times |
| 20-18 | NO_MTR_THR | R/W | 0h | No motor lock current threshold
(No motor lock current threshold (A) = NO_MTR_THR / CSA_GAIN)
0h = 0.005 V 1h = 0.0075 V 2h = 0.010 V 3h = 0.0125 V 4h = 0.020 V 5h = 0.025 V 6h = 0.030 V 7h = 0.04 V |
| 17 | MAX_VM_MODE | R/W | 0h | 0h = Latch on Overvoltage 1h = Automatic clear if voltage in bounds |
| 16-14 | MAX_VM_MOTOR | R/W | 0h | Maximum voltage for running motor
0h = No Limit 1h = 20.0 V 2h = 25.0 V 3h = 30.0 V 4h = 35.0 V 5h = 40.0 V 6h = 50.0 V 7h = 60.0 V |
| 13 | MIN_VM_MODE | R/W | 0h | 0h = Latch on Undervoltage 1h = Automatic clear if voltage in bounds |
| 12-10 | MIN_VM_MOTOR | R/W | 0h | Minimum voltage for running motor
0h = No Limit 1h = 6.0 V 2h = 7.0 V 3h = 8.0 V 4h = 9.0 V 5h = 10.0 V 6h = 12.0 V 7h = 15.0 V |
| 9-7 | AUTO_RETRY_TIMES | R/W | 0h | Number of automatic retry attempts
0h = No Limit 1h = 2 2h = 3 3h = 5 4h = 7 5h = 10 6h = 15 7h = 20 |
| 6-4 | LOCK_MIN_SPEED | R/W | 0h | Speed below which lock fault is triggered
0h = 0.5 Hz 1h = 1 Hz 2h = 2 Hz 3h = 3 Hz 4h = 5 Hz 5h = 10 Hz 6h = 15 Hz 7h = 25 Hz |
| 3-2 | ABN_LOCK_SPD_RATIO | R/W | 0h | Ratio of electrical speed between two consecutive cycles above which abnormal speed lock fault is triggered
0h = 2 1h = 4 2h = 6 3h = 8 |
| 1-0 | ZERO_DUTY_THR | R/W | 0h | Duty cycle below which target speed is zero
0h = 1% 1h = 1.5% 2h = 2.0% 3h = 2.5% |