SLLSFH8A August   2021  – December 2021 MCT8316A

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Characteristics of the SDA and SCL bus for Standard and Fast mode
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Device Interface Modes
        1. 8.3.2.1 Interface - Control and Monitoring
        2. 8.3.2.2 I2C Interface
        3. 8.3.2.3 Hardware Interface - Pin Configuration
      3. 8.3.3  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.3.1 Buck in Inductor Mode
        2. 8.3.3.2 Buck in Resistor mode
        3. 8.3.3.3 Buck Regulator with External LDO
        4. 8.3.3.4 AVDD Power Sequencing from Buck Regulator
        5. 8.3.3.5 Mixed Mode Buck Operation and Control
        6. 8.3.3.6 Buck Undervoltage Protection
        7. 8.3.3.7 Buck Overcurrent Protection
      4. 8.3.4  AVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  SPEED Control
        1. 8.3.8.1 Analog-Mode Speed Control
        2. 8.3.8.2 PWM-Mode Speed Control
        3. 8.3.8.3 I2C based Speed Control
        4. 8.3.8.4 Frequency-Mode Speed Control
      9. 8.3.9  Starting the Motor Under Different Initial Conditions
        1. 8.3.9.1 Case 1 – Motor is Stationary
        2. 8.3.9.2 Case 2 – Motor is Spinning in the Forward Direction
        3. 8.3.9.3 Case 3 – Motor is Spinning in the Reverse Direction
      10. 8.3.10 Motor Start Sequence (MSS)
        1. 8.3.10.1 Initial Speed Detect (ISD)
        2. 8.3.10.2 Motor Resynchronization
        3. 8.3.10.3 Reverse Drive
        4. 8.3.10.4 Motor Start-up
          1. 8.3.10.4.1 Align
          2. 8.3.10.4.2 Double Align
          3. 8.3.10.4.3 Initial Position Detection (IPD)
            1. 8.3.10.4.3.1 IPD Operation
            2. 8.3.10.4.3.2 IPD Release Mode
            3. 8.3.10.4.3.3 IPD Advance Angle
          4. 8.3.10.4.4 Slow First Cycle Startup
          5. 8.3.10.4.5 Open loop
          6. 8.3.10.4.6 Transition from Open to Closed Loop
      11. 8.3.11 Closed Loop Operation
        1. 8.3.11.1 120o Commutation
          1. 8.3.11.1.1 High-Side Modulation
          2. 8.3.11.1.2 Low-Side Modulation
          3. 8.3.11.1.3 Mixed Modulation
        2. 8.3.11.2 Variable Commutation (Available only in MCT8316AV)
        3. 8.3.11.3 Lead Angle Control
        4. 8.3.11.4 Closed loop accelerate
      12. 8.3.12 Speed Loop (Available only in MCT8316AV)
      13. 8.3.13 Input Power Regulation (Available only in MCT8316AV)
      14. 8.3.14 Anti-Voltage Surge (AVS)
      15. 8.3.15 Output PWM Switching Frequency
      16. 8.3.16 Fast Start-up (< 50 ms)
        1. 8.3.16.1 BEMF Threshold
        2. 8.3.16.2 Dynamic Degauss
      17. 8.3.17 Fast Deceleration
      18. 8.3.18 Active Demagnetization
        1. 8.3.18.1 Active Demagnetization in action
      19. 8.3.19 Motor Stop Options
        1. 8.3.19.1 Coast (Hi-Z) Mode
        2. 8.3.19.2 Recirculation Mode
        3. 8.3.19.3 Low-Side Braking
        4. 8.3.19.4 High-Side Braking
        5. 8.3.19.5 Active Spin-Down
      20. 8.3.20 FG Configuration
        1. 8.3.20.1 FG Output Frequency
        2. 8.3.20.2 FG Open-Loop and Lock Behavior
      21. 8.3.21 Protections
        1. 8.3.21.1  VM Supply Undervoltage Lockout
        2. 8.3.21.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.21.3  BUCK Undervoltage Lockout (BUCK_UV)
        4. 8.3.21.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.21.5  Overvoltage Protection (OVP)
        6. 8.3.21.6  Overcurrent Protection (OCP)
          1. 8.3.21.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.21.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.21.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.21.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 8.3.21.7  Buck Overcurrent Protection
        8. 8.3.21.8  Cycle-by-Cycle (CBC) Current Limit (CBC_ILIMIT)
          1. 8.3.21.8.1 CBC_ILIMIT Automatic Recovery next PWM Cycle (CBC_ILIMIT_MODE = 000xb)
          2. 8.3.21.8.2 CBC_ILIMIT Automatic Recovery Threshold Based (CBC_ILIMIT_MODE = 001xb)
          3. 8.3.21.8.3 CBC_ILIMIT Automatic Recovery after 'n' PWM Cycles (CBC_ILIMIT_MODE = 010xb)
          4. 8.3.21.8.4 CBC_ILIMIT Report Only (CBC_ILIMIT_MODE = 0110b)
          5. 8.3.21.8.5 CBC_ILIMIT Disabled (CBC_ILIMIT_MODE = 0111b or 1xxxb)
        9. 8.3.21.9  Lock Detection Current Limit (LOCK_ILIMIT)
          1. 8.3.21.9.1 LOCK_ILIMIT Latched Shutdown (LOCK_ILIMIT_MODE = 00xxb)
          2. 8.3.21.9.2 LOCK_ILIMIT Automatic Recovery (LOCK_ILIMIT_MODE = 01xxb)
          3. 8.3.21.9.3 LOCK_ILIMIT Report Only (LOCK_ILIMIT_MODE = 1000b)
          4. 8.3.21.9.4 LOCK_ILIMIT Disabled (LOCK_ILIMIT_MODE = 1xx1b)
        10. 8.3.21.10 Thermal Warning (OTW)
        11. 8.3.21.11 Thermal Shutdown (TSD)
        12. 8.3.21.12 Motor Lock (MTR_LCK)
          1. 8.3.21.12.1 MTR_LCK Latched Shutdown (MTR_LCK_MODE = 00xxb)
          2. 8.3.21.12.2 MTR_LCK Automatic Recovery (MTR_LCK_MODE= 01xxb)
          3. 8.3.21.12.3 MTR_LCK Report Only (MTR_LCK_MODE = 1000b)
          4. 8.3.21.12.4 MTR_LCK Disabled (MTR_LCK_MODE = 1xx1b)
        13. 8.3.21.13 Motor Lock Detection
          1. 8.3.21.13.1 Lock 1: Abnormal Speed (ABN_SPEED)
          2. 8.3.21.13.2 Lock 2: Loss of Sync (LOSS_OF_SYNC)
          3. 8.3.21.13.3 Lock3: No-Motor Fault (NO_MTR)
        14. 8.3.21.14 IPD Faults
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Standby Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT)
    5. 8.5 External Interface
      1. 8.5.1 DRVOFF Functionality
      2. 8.5.2 DAC outputs
      3. 8.5.3 SOX Output
      4. 8.5.4 Oscillator Source
        1. 8.5.4.1 External Clock Source (Available for MCT8316AV)
      5. 8.5.5 External Watchdog (Available only in MCT836AV)
    6. 8.6 EEPROM access and I2C interface
      1. 8.6.1 EEPROM Access
        1. 8.6.1.1 EEPROM Write
        2. 8.6.1.2 EEPROM Read
      2. 8.6.2 I2C Serial Interface (Available only in MCT8316AV)
        1. 8.6.2.1 I2C Data Word
        2. 8.6.2.2 I2C Write Operation
        3. 8.6.2.3 I2C Read Operation
        4. 8.6.2.4 Examples of MCT8316A I2C Communication Protocol Packets
        5. 8.6.2.5 Internal Buffers
        6. 8.6.2.6 CRC Byte Calculation
    7. 8.7 EEPROM (Non-Volatile) Register Map
      1. 8.7.1 Algorithm_Configuration Registers
      2. 8.7.2 Fault_Configuration Registers
      3. 8.7.3 Hardware_Configuration Registers
      4. 8.7.4 Gate_Driver_Configuration Registers
    8. 8.8 RAM (Volatile) Register Map
      1. 8.8.1 Fault_Status Registers
      2. 8.8.2 System_Status Registers
      3. 8.8.3 Algo_Control Registers
      4. 8.8.4 Device_Control Registers
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application curves
        1. 9.2.1.1 Motor startup
        2. 9.2.1.2 120o and variable commutation
        3. 9.2.1.3 Faster startup time
        4. 9.2.1.4 Setting the BEMF threshold
        5. 9.2.1.5 Maximum speed
        6. 9.2.1.6 Faster deceleration
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Support Resources
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Fault_Configuration Registers

#FAULT_CONFIGURATION_FAULT_CONFIGURATION_TABLE_1 lists the memory-mapped registers for the Fault_Configuration registers. All register offset addresses not listed in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-41 FAULT_CONFIGURATION Registers
AddressAcronymRegister NameSection
92hFAULT_CONFIG1Fault configuration 1#FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1
94hFAULT_CONFIG2Fault configuration 2#FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2

Complex bit access types are encoded to fit into small table cells. #FAULT_CONFIGURATION_FAULT_CONFIGURATION_LEGEND shows the codes that are used for access types in this section.

Table 8-42 Fault_Configuration Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

8.7.2.1 FAULT_CONFIG1 Register (Address = 92h) [Reset = 00000000h]

FAULT_CONFIG1 is shown in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1_FIGURE and described in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG1_TABLE.

Return to the Summary Table.

Register to configure fault settings1

Figure 8-67 FAULT_CONFIG1 Register
3130292827262524
PARITYRESERVEDNO_MTR_DEG_TIMECBC_ILIMIT_MODE
R/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
CBC_ILIMIT_MODELOCK_ILIMITLOCK_ILIMIT_MODE
R/W-0hR/W-0hR/W-0h
15141312111098
LOCK_ILIMIT_MODELOCK_ILIMIT_DEGCBC_RETRY_PWM_CYC
R/W-0hR/W-0hR/W-0h
76543210
RESERVEDMTR_LCK_MODELCK_RETRY
R/W-0hR/W-0hR/W-0h
Table 8-43 FAULT_CONFIG1 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30RESERVEDR/W0h Reserved
29-27NO_MTR_DEG_TIMER/W0h No motor detect deglitch time

0h = 1 ms

1h = 10 ms

2h = 25 ms

3h = 50 ms

4h = 100 ms

5h = 250 ms

6h = 500 ms

7h = 1000 ms

26-23CBC_ILIMIT_MODER/W0h Cycle by cycle current limit

0h = Automatic recovery next PWM cycle; nFAULT active; driver is in recirculation mode

1h = Automatic recovery next PWM cycle; nFAULT inactive; driver is in recirculation mode

2h = Automatic recovery if VSOX < ILIMIT; nFAULT active; driver is in recirculation mode (Only available with high-side modulation)

3h = Automatic recovery if VSOX < ILIMIT; nFAULT inactive; driver is in recirculation mode (Only available with high-side modulation)

4h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT active; driver is in recirculation mode

5h = Automatic recovery after CBC_RETRY_PWM_CYC; nFAULT inactive; driver is in recirculation mode

6h = VSOX > ILIMIT is report only but no action is taken

7h = Cycle by Cycle limit is disabled

8h = Cycle by Cycle limit is disabled

9h = Cycle by Cycle limit is disabled

Ah = Cycle by Cycle limit is disabled

Bh = Cycle by Cycle limit is disabled

Ch = Cycle by Cycle limit is disabled

Dh = Cycle by Cycle limit is disabled

Eh = Cycle by Cycle limit is disabled

Fh = Cycle by Cycle limit is disabled

22-19LOCK_ILIMITR/W0h Lock detection current limit (Lock detection current limit (A) = LOCK_ILIMIT / CSA_GAIN)

0h = N/A

1h = 0.1 V

2h = 0.2 V

3h = 0.3 V

4h = 0.4 V

5h = 0.5 V

6h = 0.6 V

7h = 0.7 V

8h = 0.8 V

9h = 0.9 V

Ah = 1 V

Bh = 1.1 V

Ch = 1.2 V

Dh = 1.3 V

Eh = 1.4 V

Fh = 1.5 V

18-15LOCK_ILIMIT_MODER/W0h Lock detection current limit mode

0h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is tristated

1h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in recirculation mode

2h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in high-side brake mode (All high-side FETs are turned ON)

3h = Ilimit lock detection causes latched fault; nFAULT active; Gate driver is in low-side brake mode (All low-side FETs are turned ON)

4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated

5h = Automatic recovery after tLCK_RETRY; Gate driver is in recirculation mode

6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-side brake mode (All high-side FETs are turned ON)

7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-side brake mode (All low-side FETs are turned ON)

8h = Ilimit lock detection is in report only but no action is taken

9h = Ilimit lock detection is disabled

Ah = Ilimit lock detection is disabled

Bh = Ilimit lock detection is disabled

Ch = Ilimit lock detection is disabled

Dh = Ilimit lock detection is disabled

Eh = Ilimit lock detection is disabled

Fh = Ilimit lock detection is disabled

14-11LOCK_ILIMIT_DEGR/W0h Lock detection current limit deglitch time

0h = 1 ms

1h = 2 ms

2h = 5 ms

3h = 10 ms

4h = 25 ms

5h = 50 ms

6h = 75 ms

7h = 100 ms

8h = 250 ms

9h = 500 ms

Ah = 1 s

Bh = 2.5 s

Ch = 5 s

Dh = 10 s

Eh = 25 s

Fh = 50 s

10-8CBC_RETRY_PWM_CYCR/W0h Number of PWM cycles for CBC current limit to retry

0h = 0

1h = 1

2h = 2

3h = 3

4h = 4

5h = 5

6h = 6

7h = 7

7RESERVEDR/W0h Reserved
6-3MTR_LCK_MODER/W0h Motor lock mode

0h = Motor lock detection causes latched fault; nFAULT active; Gate driver is tristated

1h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in recirculation mode

2h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in high-side brake mode (All high-side FETs are turned ON)

3h = Motor lock detection causes latched fault; nFAULT active; Gate driver is in low-side brake mode (All low-side FETs are turned ON)

4h = Automatic recovery after tLCK_RETRY; Gate driver is tristated

5h = Automatic recovery after tLCK_RETRY; Gate driver is in recirculation mode

6h = Automatic recovery after tLCK_RETRY; Gate driver is in high-side brake mode (All high-side FETs are turned ON)

7h = Automatic recovery after tLCK_RETRY; Gate driver is in low-side brake mode (All low-side FETs are turned ON)

8h = Motor lock detection is in report only but no action is taken

9h = Motor lock detection is disabled

Bh = Motor lock detection is disabled

Ch = Motor lock detection is disabled

Dh = Motor lock detection is disabled

Eh = Motor lock detection is disabled

Fh = Motor lock detection is disabled

2-0LCK_RETRYR/W0h Lock retry time

0h = 100 ms

1h = 500 ms

2h = 1000 ms

3h = 2000 ms

4h = 3000 ms

5h = 5000 ms

6h = 7500 ms

7h = 10000 ms

8.7.2.2 FAULT_CONFIG2 Register (Address = 94h) [Reset = 00000000h]

FAULT_CONFIG2 is shown in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2_FIGURE and described in #FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIGURATION_FAULT_CONFIG2_TABLE.

Return to the Summary Table.

Register to configure fault settings2

Figure 8-68 FAULT_CONFIG2 Register
3130292827262524
PARITYLOCK1_ENLOCK2_ENLOCK3_ENLOCK_ABN_SPEED
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
LOSS_SYNC_TIMESNO_MTR_THRMAX_VM_MODEMAX_VM_MOTOR
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
MAX_VM_MOTORMIN_VM_MODEMIN_VM_MOTORAUTO_RETRY_TIMES
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
AUTO_RETRY_TIMESLOCK_MIN_SPEEDABN_LOCK_SPD_RATIOZERO_DUTY_THR
R/W-0hR/W-0hR/W-0hR/W-0h
Table 8-44 FAULT_CONFIG2 Register Field Descriptions
BitFieldTypeResetDescription
31PARITYR/W0h Parity bit
30LOCK1_ENR/W0h Lock 1 (Abnormal Speed) Enable

0h = Disable

1h = Enable

29LOCK2_ENR/W0h Lock 2 (Loss of Sync) Enable

0h = Disable

1h = Enable

28LOCK3_ENR/W0h Lock 3 (No Motor) Enable

0h = Disable

1h = Enable

27-24LOCK_ABN_SPEEDR/W0h Abnormal speed lock threshold

0h = 250 Hz

1h = 500 Hz

2h = 750 Hz

3h = 1000 Hz

4h = 1250 Hz

5h = 1500 Hz

6h = 1750 Hz

7h = 2000 Hz

8h = 2250 Hz

9h = 2500 Hz

Ah = 2750 Hz

Bh = 3000 Hz

Ch = 3250 Hz

Dh = 3500 Hz

Eh = 3750 Hz

Fh = 4000 Hz

23-21LOSS_SYNC_TIMESR/W0h Number of times sync lost for loss of sync lock fault

0h = Trigger after losing sync 2 times

1h = Trigger after losing sync 3 times

2h = Trigger after losing sync 4 times

3h = Trigger after losing sync 5 times

4h = Trigger after losing sync 6 times

5h = Trigger after losing sync 7 times

6h = Trigger after losing sync 8 times

7h = Trigger after losing sync 9 times

20-18NO_MTR_THRR/W0h No motor lock current threshold (No motor lock current threshold (A) = NO_MTR_THR / CSA_GAIN)

0h = 0.005 V

1h = 0.0075 V

2h = 0.010 V

3h = 0.0125 V

4h = 0.020 V

5h = 0.025 V

6h = 0.030 V

7h = 0.04 V

17MAX_VM_MODER/W0h

0h = Latch on Overvoltage

1h = Automatic clear if voltage in bounds

16-14MAX_VM_MOTORR/W0h Maximum voltage for running motor

0h = No Limit

1h = 20.0 V

2h = 25.0 V

3h = 30.0 V

4h = 35.0 V

5h = 40.0 V

6h = 50.0 V

7h = 60.0 V

13MIN_VM_MODER/W0h

0h = Latch on Undervoltage

1h = Automatic clear if voltage in bounds

12-10MIN_VM_MOTORR/W0h Minimum voltage for running motor

0h = No Limit

1h = 6.0 V

2h = 7.0 V

3h = 8.0 V

4h = 9.0 V

5h = 10.0 V

6h = 12.0 V

7h = 15.0 V

9-7AUTO_RETRY_TIMESR/W0h Number of automatic retry attempts

0h = No Limit

1h = 2

2h = 3

3h = 5

4h = 7

5h = 10

6h = 15

7h = 20

6-4LOCK_MIN_SPEEDR/W0h Speed below which lock fault is triggered

0h = 0.5 Hz

1h = 1 Hz

2h = 2 Hz

3h = 3 Hz

4h = 5 Hz

5h = 10 Hz

6h = 15 Hz

7h = 25 Hz

3-2ABN_LOCK_SPD_RATIOR/W0h Ratio of electrical speed between two consecutive cycles above which abnormal speed lock fault is triggered

0h = 2

1h = 4

2h = 6

3h = 8

1-0ZERO_DUTY_THRR/W0h Duty cycle below which target speed is zero

0h = 1%

1h = 1.5%

2h = 2.0%

3h = 2.5%