SLASEU5A October   2019  – February 2021 MSP430F5438A-ET

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Functional Block Diagram
  5. 5Revision History
  6. 6Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  7. 7Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Active Mode Supply Current Into VCC Excluding External Current
    4. 7.4  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    5. 7.5  Thermal Resistance Characteristics
    6. 7.6  Schmitt-Trigger Inputs – General Purpose I/O
    7. 7.7  Inputs – Ports P1 and P2
    8. 7.8  Leakage Current – General Purpose I/O
    9. 7.9  Outputs – General Purpose I/O (Full Drive Strength)
    10. 7.10 Outputs – General Purpose I/O (Reduced Drive Strength)
    11. 7.11 Output Frequency – General Purpose I/O
    12. 7.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    13. 7.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    14. 7.14 Crystal Oscillator, XT1, Low-Frequency Mode
    15. 7.15 Crystal Oscillator, XT1, High-Frequency Mode
    16. 7.16 Crystal Oscillator, XT2
    17. 7.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 7.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 7.19 DCO Frequency
    20. 7.20 PMM, Brownout Reset (BOR)
    21. 7.21 PMM, Core Voltage
    22. 7.22 PMM, SVS High Side
    23. 7.23 PMM, SVM High Side
    24. 7.24 PMM, SVS Low Side
    25. 7.25 PMM, SVM Low Side
    26. 7.26 Wakeup From Low-Power Modes and Reset
    27. 7.27 Timer_A
    28. 7.28 Timer_B
    29. 7.29 USCI (UART Mode) Recommended Operating Conditions
    30. 7.30 USCI (UART Mode)
    31. 7.31 USCI (SPI Master Mode) Recommended Operating Conditions
    32. 7.32 USCI (SPI Master Mode)
    33. 7.33 USCI (SPI Slave Mode)
    34. 7.34 USCI (I2C Mode)
    35. 7.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 7.36 12-Bit ADC, Timing Parameters
    37. 7.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 7.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 7.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 7.40 REF, External Reference
    41. 7.41 REF, Built-In Reference
    42. 7.42 Flash Memory
    43. 7.43 JTAG and Spy-Bi-Wire Interface
  8. 8Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
    3. 8.3  Interrupt Vector Addresses
    4. 8.4  Memory Organization
    5. 8.5  Bootloader (BSL)
    6. 8.6  JTAG Operation
      1. 8.6.1 JTAG Standard Interface
      2. 8.6.2 Spy-Bi-Wire Interface
    7. 8.7  Flash Memory
    8. 8.8  RAM Memory
    9. 8.9  Peripherals
      1. 8.9.1  Digital I/O
      2. 8.9.2  Oscillator and System Clock
      3. 8.9.3  Power Management Module (PMM)
      4. 8.9.4  Hardware Multiplier (MPY)
      5. 8.9.5  Real-Time Clock (RTC_A)
      6. 8.9.6  Watchdog Timer (WDT_A)
      7. 8.9.7  System Module (SYS)
      8. 8.9.8  DMA Controller
      9. 8.9.9  Universal Serial Communication Interface (USCI)
      10. 8.9.10 TA0
      11. 8.9.11 TA1
      12. 8.9.12 TB0
      13. 8.9.13 ADC12_A
      14. 8.9.14 CRC16
      15. 8.9.15 REF Voltage Reference
      16. 8.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 8.9.17 Peripheral File Map
      18. 8.9.18 Input/Output Diagrams
        1. 8.9.18.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
        2. 8.9.18.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
        3. 8.9.18.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
        4. 8.9.18.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
        5. 8.9.18.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
        6. 8.9.18.6  Port P5, P5.2, Input/Output With Schmitt Trigger
        7. 8.9.18.7  Port P5, P5.3, Input/Output With Schmitt Trigger
        8. 8.9.18.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
        9. 8.9.18.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
        10. 8.9.18.10 Port P7, P7.0, Input/Output With Schmitt Trigger
        11. 8.9.18.11 Port P7, P7.1, Input/Output With Schmitt Trigger
        12. 8.9.18.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
        13. 8.9.18.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
        14. 8.9.18.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
        15. 8.9.18.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
        16. 8.9.18.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
        17. 8.9.18.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
        18. 8.9.18.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
        19. 8.9.18.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    10. 8.10 Device Descriptors (TLV)
  9. 9Device and Documentation Support
    1. 9.1 Trademarks
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Support Resources
    4. 9.4 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.32 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
fUSCI USCI input clock frequency SMCLK, ACLK,
Duty cycle = 50% ± 10%		 fSYSTEM MHz
tSU,MI SOMI input data setup time PMMCOREV = 0 1.8 V 55 ns
3.0 V 38
PMMCOREV = 3 2.4 V 30 ns
3.0 V 25
tHD,MI SOMI input data hold time PMMCOREV = 0 1.8 V 0 ns
3.0 V 0
PMMCOREV = 3 2.4 V 0 ns
3.0 V 0
tVALID,MO SIMO output data valid time(2) UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 0		 1.8 V 20 ns
3.0 V 18
UCLK edge to SIMO valid,
CL = 20 pF, PMMCOREV = 3		 2.4 V 16 ns
3.0 V 15
tHD,MO SIMO output data hold time(3) CL = 20 pF, PMMCOREV = 0 1.8 V -10 ns
3.0 V -8
CL = 20 pF, PMMCOREV = 3 2.4 V -10 ns
3.0 V -8
(1) fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 7-12 and Figure 7-13.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 7-12 and Figure 7-13.
GUID-9996CABD-C400-474E-A132-3802605E4A9B-low.gif Figure 7-12 SPI Master Mode, CKPH = 0
GUID-439FE066-BA8F-4A78-9250-A155807AF302-low.gif Figure 7-13 SPI Master Mode, CKPH = 1