SLASEU5A October   2019  – February 2021 MSP430F5438A-ET

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Functional Block Diagram
  5. 5Revision History
  6. 6Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Signal Descriptions
  7. 7Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  Recommended Operating Conditions
    3. 7.3  Active Mode Supply Current Into VCC Excluding External Current
    4. 7.4  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    5. 7.5  Thermal Resistance Characteristics
    6. 7.6  Schmitt-Trigger Inputs – General Purpose I/O
    7. 7.7  Inputs – Ports P1 and P2
    8. 7.8  Leakage Current – General Purpose I/O
    9. 7.9  Outputs – General Purpose I/O (Full Drive Strength)
    10. 7.10 Outputs – General Purpose I/O (Reduced Drive Strength)
    11. 7.11 Output Frequency – General Purpose I/O
    12. 7.12 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    13. 7.13 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    14. 7.14 Crystal Oscillator, XT1, Low-Frequency Mode
    15. 7.15 Crystal Oscillator, XT1, High-Frequency Mode
    16. 7.16 Crystal Oscillator, XT2
    17. 7.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 7.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 7.19 DCO Frequency
    20. 7.20 PMM, Brownout Reset (BOR)
    21. 7.21 PMM, Core Voltage
    22. 7.22 PMM, SVS High Side
    23. 7.23 PMM, SVM High Side
    24. 7.24 PMM, SVS Low Side
    25. 7.25 PMM, SVM Low Side
    26. 7.26 Wakeup From Low-Power Modes and Reset
    27. 7.27 Timer_A
    28. 7.28 Timer_B
    29. 7.29 USCI (UART Mode) Recommended Operating Conditions
    30. 7.30 USCI (UART Mode)
    31. 7.31 USCI (SPI Master Mode) Recommended Operating Conditions
    32. 7.32 USCI (SPI Master Mode)
    33. 7.33 USCI (SPI Slave Mode)
    34. 7.34 USCI (I2C Mode)
    35. 7.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 7.36 12-Bit ADC, Timing Parameters
    37. 7.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 7.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 7.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 7.40 REF, External Reference
    41. 7.41 REF, Built-In Reference
    42. 7.42 Flash Memory
    43. 7.43 JTAG and Spy-Bi-Wire Interface
  8. 8Detailed Description
    1. 8.1  CPU
    2. 8.2  Operating Modes
    3. 8.3  Interrupt Vector Addresses
    4. 8.4  Memory Organization
    5. 8.5  Bootloader (BSL)
    6. 8.6  JTAG Operation
      1. 8.6.1 JTAG Standard Interface
      2. 8.6.2 Spy-Bi-Wire Interface
    7. 8.7  Flash Memory
    8. 8.8  RAM Memory
    9. 8.9  Peripherals
      1. 8.9.1  Digital I/O
      2. 8.9.2  Oscillator and System Clock
      3. 8.9.3  Power Management Module (PMM)
      4. 8.9.4  Hardware Multiplier (MPY)
      5. 8.9.5  Real-Time Clock (RTC_A)
      6. 8.9.6  Watchdog Timer (WDT_A)
      7. 8.9.7  System Module (SYS)
      8. 8.9.8  DMA Controller
      9. 8.9.9  Universal Serial Communication Interface (USCI)
      10. 8.9.10 TA0
      11. 8.9.11 TA1
      12. 8.9.12 TB0
      13. 8.9.13 ADC12_A
      14. 8.9.14 CRC16
      15. 8.9.15 REF Voltage Reference
      16. 8.9.16 Embedded Emulation Module (EEM) (L Version)
      17. 8.9.17 Peripheral File Map
      18. 8.9.18 Input/Output Diagrams
        1. 8.9.18.1  Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
        2. 8.9.18.2  Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
        3. 8.9.18.3  Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
        4. 8.9.18.4  Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
        5. 8.9.18.5  Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
        6. 8.9.18.6  Port P5, P5.2, Input/Output With Schmitt Trigger
        7. 8.9.18.7  Port P5, P5.3, Input/Output With Schmitt Trigger
        8. 8.9.18.8  Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
        9. 8.9.18.9  Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
        10. 8.9.18.10 Port P7, P7.0, Input/Output With Schmitt Trigger
        11. 8.9.18.11 Port P7, P7.1, Input/Output With Schmitt Trigger
        12. 8.9.18.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
        13. 8.9.18.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
        14. 8.9.18.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
        15. 8.9.18.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
        16. 8.9.18.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
        17. 8.9.18.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
        18. 8.9.18.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
        19. 8.9.18.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    10. 8.10 Device Descriptors (TLV)
  9. 9Device and Documentation Support
    1. 9.1 Trademarks
    2. 9.2 Electrostatic Discharge Caution
    3. 9.3 Support Resources
    4. 9.4 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.10 Device Descriptors (TLV)

Table 8-58 lists the complete contents of the device descriptor tag-length-value (TLV) structure for each device type.

Table 8-58 Device Descriptors (1)
DESCRIPTION ADDRESS SIZE (bytes) VALUE
Info Block Info length 01A00h 1 06h
CRC length 01A01h 1 06h
CRC value 01A02h 2 per unit
Device ID 01A04h 1 05h
Device ID 01A05h 1 80h
Hardware revision 01A06h 1 per unit
Firmware revision 01A07h 1 per unit
Die Record Die Record Tag 01A08h 1 08h
Die Record length 01A09h 1 0Ah
Lot/Wafer ID 01A0Ah 4 per unit
Die X position 01A0Eh 2 per unit
Die Y position 01A10h 2 per unit
Test results 01A12h 2 per unit
ADC12 Calibration ADC12 Calibration Tag 01A14h 1 11h
ADC12 Calibration length 01A15h 1 10h
ADC Gain Factor 01A16h 2 per unit
ADC Offset 01A18h 2 per unit
ADC 1.5-V ReferenceTemp. Sensor 30°C 01A1Ah 2 per unit
ADC 1.5-V ReferenceTemp. Sensor 85°C 01A1Ch 2 per unit
ADC 2.0-V ReferenceTemp. Sensor 30°C 01A1Eh 2 per unit
ADC 2.0-V ReferenceTemp. Sensor 85°C 01A20h 2 per unit
ADC 2.5-V ReferenceTemp. Sensor 30°C 01A22h 2 per unit
ADC 2.5-V ReferenceTemp. Sensor 85°C 01A24h 2 per unit
REF Calibration REF Calibration Tag 01A26h 1 12h
REF Calibration length 01A27h 1 06h
REF 1.5-V Reference 01A28h 2 per unit
REF 2.0-V Reference 01A2Ah 2 per unit
REF 2.5-V Reference 01A2Ch 2 per unit
Peripheral Descriptor Peripheral Descriptor Tag 01A2Eh 1 02h
Peripheral Descriptor Length 01A2Fh 1 61h
Memory 1 2 08h8Ah
Memory 2 2 0Ch86h
Memory 3 2 0Eh30h
Memory 4 2 2Eh98h
Memory 5 0/1 NA
delimiter 1 00h
Peripheral count 1 21h
MSP430CPUXV2 2 00h23h
SBW 2 00h0Fh
EEM-8 2 00h05h
TI BSL 2 00hFCh
Package 2 00h1Fh
SFR 2 10h41h
PMM 2 02h30h
FCTL 2 02h38h
CRC16-straight 2 01h3Ch
CRC16-bit reversed 2 00h3Dh
RAMCTL 2 00h44h
WDT_A 2 00h40h
UCS 2 01h48h
SYS 2 02h42h
REF 2 03hA0h
Port 1/2 2 05h51h
Port 3/4 2 02h52h
Port 5/6 2 02h53h
Port 7/8 2 02h54h
Port 9/10 2 02h55h
Port 11/12 2 02h56h
JTAG 2 08h5Fh
TA0 2 02h62h
TA1 2 04h61h
TB0 2 04h67h
RTC 2 0Eh68h
MPY32 2 02h85h
DMA-3 2 04h47h
USCI_A/B 2 0Ch90h
USCI_A/B 2 04h90h
USCI_A/B 2 04h90h
USCI_A/B 2 04h90h
ADC12_A 2 08hD1h
Interrupts TB0.CCIFG0 1 64h
TB0.CCIFG1..6 1 65h
WDTIFG 1 40h
USCI_A0 1 90h
USCI_B0 1 91h
ADC12_A 1 D0h
TA0.CCIFG0 1 60h
TA0.CCIFG1..4 1 61h
USCI_A2 1 94h
USCI_B2 1 95h
DMA 1 46h
TA1.CCIFG0 1 62h
TA1.CCIFG1..2 1 63h
P1 1 50h
USCI_A1 1 92h
USCI_B1 1 93h
USCI_A3 1 96h
USCI_B3 1 97h
P2 1 51h
RTC_A 1 68h
delimiter 1 00h
(1) NA = Not applicable.