Achieving optimized performance with a high-frequency amplifier like the OPA4830 requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include:

a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability. On the noninverting input, parasitic capacitance on the output and inverting input pins can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, open a window around the signal I/O pins in all of the ground and power planes around those pins. Otherwise, keep ground and power planes unbroken elsewhere on the board.

b) Minimize the distance (< 0.25”) from the power-supply pins to high-frequency 0.1μF decoupling capacitors. At the device pins, the ground and power-plane layout cannot be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Each power-supply connection can always be decoupled with one of these capacitors. An optional supply decoupling capacitor (0.1μF) across the two power supplies (for bipolar operation) improves 2nd-harmonic distortion performance. Larger (2.2μF to 6.8μF) decoupling capacitors, effective at lower frequency, can also be used on the main supply pins. These can be placed somewhat farther from the device and can be shared among several devices in the same area of the PCB.

c) Careful selection and placement of external components preserve the high-frequency performance. Resistors needs to be a very low-reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high-frequency performance. Again, keep the leads and PCB traces as short as possible. Never use wire-wound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, can also be placed close to the package. Where double-side component mounting is allowed, place the feedback resistor directly under the package on the other side of the board between the output and inverting input pins. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5kΩ, this parasitic capacitance can add a pole and/or zero below 500MHz that can effect circuit operation. Keep resistor values as low as possible consistent with load driving considerations. The 750Ω feedback used in the Typical Characteristics is a good starting point for design.

d) Connections to other wide band devices on the board can be made with short direct traces or through on board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) can be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set R_S from the typical characteristic curve Recommended R_S vs Capacitive Load (Figure 6-14, Figure 6-36, or Figure 6-59). Low parasitic capacitive loads (< 5pF) do not need an R_S because the OPA4830 is nominally compensated to operate with a 2pF parasitic load. Higher parasitic capacitive loads without an R_S are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using micro strip or strip line techniques (consult an ECL design handbook for micro strip and strip line layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined (based on board material and trace dimensions), a matching series resistor into the trace from the output of the OPA4830 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance can be set to match the trace impedance. If the 6dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value as shown in the typical characteristic curve Recommended R_S vs Capacitive Load (Figure 6-14, Figure 6-36, or Figure 6-59). This configuration does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there can be some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.

e) Do not socket a high-speed part. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that makes achieving a smooth, stable frequency response impossible. Best results are obtained by soldering the OPA4830 directly onto the board.